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| h8/3927 series h8/3927, h8/3926, h8/3925, h8/3924 hardware manual omc942723159
preface the h8/300l series of single-chip microcomputers has the high-speed h8/300l cpu at its core, with many necessary peripheral functions on-chip. the h8/300l cpu instruction set is compatible with the h8/300 cpu. the h8/3927 series has a system-on-a-chip architecture that includes such peripheral functions as a d/a converter, ten timers, a 14-bit pwm, a two-channel serial communication interface, and an a/d converter. this makes it ideal for use in advanced control systems. this manual describes the hardware of the h8/3927 series. for details on the h8/3927 series instruction set, refer to the h8/300l series programming manual. contents section 1 overview ......................................................................................................... 1 1.1 overview......................................................................................................................... 1 1.2 internal block diagram .................................................................................................. 5 1.3 pin arrangement and functions ..................................................................................... 6 1.3.1 pin arrangement................................................................................................. 6 1.3.2 pin functions ...................................................................................................... 8 section 2 cpu ................................................................................................................... 13 2.1 overview......................................................................................................................... 13 2.1.1 features............................................................................................................... 13 2.1.2 address space..................................................................................................... 14 2.1.3 register configuration........................................................................................ 14 2.2 register descriptions...................................................................................................... 15 2.2.1 general registers................................................................................................ 15 2.2.2 control registers ................................................................................................ 15 2.2.3 initial register values ........................................................................................ 17 2.3 data formats................................................................................................................... 17 2.3.1 data formats in general registers ..................................................................... 18 2.3.2 memory data formats........................................................................................ 19 2.4 addressing modes .......................................................................................................... 20 2.4.1 addressing modes .............................................................................................. 20 2.4.2 effective address calculation ............................................................................ 22 2.5 instruction set................................................................................................................. 26 2.5.1 data transfer instructions .................................................................................. 28 2.5.2 arithmetic operations ........................................................................................ 30 2.5.3 logic operations ................................................................................................ 31 2.5.4 shift operations .................................................................................................. 31 2.5.5 bit manipulations ............................................................................................... 33 2.5.6 branching instructions........................................................................................ 37 2.5.7 system control instructions ............................................................................... 39 2.5.8 block data transfer instruction ......................................................................... 40 2.6 basic operational timing............................................................................................... 42 2.6.1 access to on-chip memory (ram, rom) ....................................................... 42 2.6.2 access to on-chip peripheral modules ............................................................. 43 2.7 cpu states ...................................................................................................................... 45 2.7.1 overview............................................................................................................. 45 2.7.2 program execution state ................................................................................... 46 2.7.3 program halt state.............................................................................................. 46 2.7.4 exception-handling state................................................................................... 46 2.8 memory map .................................................................................................................. 47 2.8.1 memory map ...................................................................................................... 47 2.9 application notes ........................................................................................................... 48 2.9.1 notes on data access ......................................................................................... 48 2.9.2 notes on bit manipulation.................................................................................. 50 2.9.3 notes on use of the eepmov instruction......................................................... 56 section 3 exception handling ...................................................................................... 57 3.1 overview......................................................................................................................... 57 3.2 reset ............................................................................................................................ 57 3.2.1 overview............................................................................................................. 57 3.2.2 reset sequence ................................................................................................... 57 3.2.3 interrupt immediately after reset....................................................................... 59 3.3 interrupts......................................................................................................................... 59 3.3.1 overview............................................................................................................. 59 3.3.2 interrupt control registers ................................................................................. 61 3.3.3 external interrupts .............................................................................................. 71 3.3.4 internal interrupts ............................................................................................... 72 3.3.5 interrupt operations............................................................................................ 73 3.3.6 interrupt response time..................................................................................... 78 3.4 application notes ........................................................................................................... 79 3.4.1 notes on stack area use .................................................................................... 79 3.4.2 notes on rewriting port mode registers ........................................................... 80 section 4 clock pulse generators ............................................................................... 83 4.1 overview......................................................................................................................... 83 4.1.1 block diagram.................................................................................................... 83 4.1.2 system clock and subclock ............................................................................... 83 4.2 system clock generator ................................................................................................. 84 4.3 subclock generator ........................................................................................................ 87 4.4 prescalers ........................................................................................................................ 89 4.5 note on oscillators ......................................................................................................... 90 section 5 power-down modes ..................................................................................... 91 5.1 overview......................................................................................................................... 91 5.1.1 system control registers ................................................................................... 94 5.2 sleep mode ..................................................................................................................... 98 5.2.1 transition to sleep mode.................................................................................... 98 5.2.2 clearing sleep mode .......................................................................................... 98 5.2.3 clock frequency in sleep (medium-speed) mode ............................................ 98 5.3 standby mode................................................................................................................. 99 5.3.1 transition to standby mode ............................................................................... 99 5.3.2 clearing standby mode ...................................................................................... 99 5.3.3 oscillator settling time after standby mode is cleared.................................... 100 5.4 watch mode.................................................................................................................... 101 5.4.1 transition to watch mode .................................................................................. 101 5.4.2 clearing watch mode......................................................................................... 101 5.4.3 oscillator settling time after watch mode is cleared ...................................... 101 5.5 subsleep mode................................................................................................................ 102 5.5.1 transition to subsleep mode .............................................................................. 102 5.5.2 clearing subsleep mode..................................................................................... 102 5.6 subactive mode .............................................................................................................. 103 5.6.1 transition to subactive mode............................................................................. 103 5.6.2 clearing subactive mode ................................................................................... 103 5.6.3 operating frequency in subactive mode ........................................................... 103 5.7 active (medium-speed) mode ....................................................................................... 104 5.7.1 transition to active (medium-speed) mode ..................................................... 104 5.7.2 clearing active (medium-speed) mode ............................................................ 104 5.7.3 operating frequency in active (medium-speed) mode .................................... 104 5.8 direct transfer................................................................................................................ 105 section 6 rom ................................................................................................................. 107 6.1 overview......................................................................................................................... 107 6.1.1 block diagram.................................................................................................... 107 6.2 prom mode................................................................................................................... 108 6.2.1 setting to prom mode ..................................................................................... 108 6.2.2 socket adapter pin arrangement and memory map ......................................... 108 6.3 programming .................................................................................................................. 111 6.3.1 writing and verifying......................................................................................... 111 6.3.2 programming precautions................................................................................... 116 6.4 reliability of programmed data..................................................................................... 117 section 7 ram ................................................................................................................. 119 7.1 overview......................................................................................................................... 119 7.1.1 block diagram.................................................................................................... 119 section 8 i/o ports ........................................................................................................... 121 8.1 overview......................................................................................................................... 121 8.2 port 1 ............................................................................................................................ 123 8.2.1 overview............................................................................................................. 123 8.2.2 register configuration and description ............................................................. 123 8.2.3 pin functions ...................................................................................................... 127 8.2.4 pin states ............................................................................................................ 128 8.2.5 mos input pull-up............................................................................................. 128 8.3 port 3 ............................................................................................................................ 129 8.3.1 overview............................................................................................................. 129 8.3.2 register configuration and description ............................................................. 129 8.3.3 pin functions ...................................................................................................... 134 8.3.4 pin states ............................................................................................................ 136 8.3.5 mos input pull-up............................................................................................. 136 8.4 port 4 ............................................................................................................................ 137 8.4.1 overview............................................................................................................. 137 8.4.2 register configuration and description ............................................................. 137 8.4.3 pin functions ...................................................................................................... 138 8.4.4 pin states ............................................................................................................ 138 8.5 port 5 ............................................................................................................................ 139 8.5.1 overview............................................................................................................. 139 8.5.2 register configuration and description ............................................................. 139 8.5.3 pin functions ...................................................................................................... 141 8.5.4 pin states ............................................................................................................ 142 8.5.5 mos input pull-up............................................................................................. 142 8.6 port 6 ............................................................................................................................ 143 8.6.1 overview............................................................................................................. 143 8.6.2 register configuration and description ............................................................. 143 8.6.3 pin functions ...................................................................................................... 145 8.6.4 pin states ............................................................................................................ 145 8.6.5 operation ............................................................................................................ 146 8.7 port 7 ............................................................................................................................ 148 8.7.1 overview............................................................................................................. 148 8.7.2 register configuration and description ............................................................. 148 8.7.3 pin functions ...................................................................................................... 150 8.7.4 pin states ............................................................................................................ 150 8.8 port 8 ............................................................................................................................ 151 8.8.1 overview............................................................................................................. 151 8.8.2 register configuration and description ............................................................. 151 8.8.3 pin functions ...................................................................................................... 153 8.8.4 pin states ............................................................................................................ 154 8.9 port b ............................................................................................................................ 155 8.9.1 overview............................................................................................................. 155 8.9.2 register configuration and description ............................................................. 155 8.9.3 pin functions ...................................................................................................... 156 8.9.4 pin states ............................................................................................................ 156 8.10 port c ............................................................................................................................ 157 8.10.1 overview............................................................................................................. 157 8.10.2 register configuration and description ............................................................. 157 8.10.3 pin functions ...................................................................................................... 158 8.10.4 pin states ............................................................................................................ 158 section 9 timers ............................................................................................................... 159 9.1 overview......................................................................................................................... 159 9.2 timer a........................................................................................................................... 161 9.2.1 overview............................................................................................................. 161 9.2.2 register descriptions.......................................................................................... 163 9.2.3 timer operation.................................................................................................. 165 9.2.4 timer a operation states ................................................................................... 166 9.3 timer b1......................................................................................................................... 167 9.3.1 overview............................................................................................................. 167 9.3.2 register descriptions.......................................................................................... 168 9.3.3 timer operation.................................................................................................. 170 9.3.4 timer b1 operation states ................................................................................. 171 9.4 timer b2......................................................................................................................... 172 9.4.1 overview............................................................................................................. 172 9.4.2 register descriptions.......................................................................................... 173 9.4.3 timer operation.................................................................................................. 175 9.4.4 timer b2 operation states ................................................................................. 176 9.5 timer b3......................................................................................................................... 177 9.5.1 overview............................................................................................................. 177 9.5.2 register descriptions.......................................................................................... 178 9.5.3 timer operation.................................................................................................. 180 9.5.4 timer b3 operation states ................................................................................. 181 9.6 timer c........................................................................................................................... 182 9.6.1 overview............................................................................................................. 182 9.6.2 register descriptions.......................................................................................... 183 9.6.3 timer operation.................................................................................................. 186 9.6.4 timer c operation states ................................................................................... 187 9.7 timer e ........................................................................................................................... 188 9.7.1 overview............................................................................................................. 188 9.7.2 register descriptions.......................................................................................... 189 9.7.3 timer operation.................................................................................................. 192 9.7.4 timer e operation states.................................................................................... 194 9.8 timer v........................................................................................................................... 195 9.8.1 overview............................................................................................................. 195 9.8.2 register descriptions.......................................................................................... 198 9.8.3 timer operation.................................................................................................. 204 9.8.4 timer v operation modes.................................................................................. 209 9.8.5 interrupt sources................................................................................................. 209 9.8.6 application examples......................................................................................... 210 9.8.7 application notes ............................................................................................... 212 9.9 timer x........................................................................................................................... 218 9.9.1 overview............................................................................................................. 218 9.9.2 register descriptions.......................................................................................... 222 9.9.3 cpu interface ..................................................................................................... 233 9.9.4 timer operation.................................................................................................. 236 9.9.5 timer x operation modes.................................................................................. 245 9.9.6 interrupt sources................................................................................................. 245 9.9.7 timer x application example............................................................................ 246 9.9.8 application notes ............................................................................................... 247 9.10 timer y........................................................................................................................... 252 9.10.1 overview............................................................................................................. 252 9.10.2 register descriptions.......................................................................................... 253 9.10.3 cpu interface ..................................................................................................... 256 9.10.4 timer operation.................................................................................................. 259 9.10.5 timer y operation states ................................................................................... 260 9.11 watchdog timer ............................................................................................................. 261 9.11.1 overview............................................................................................................. 261 9.11.2 register descriptions.......................................................................................... 262 9.11.3 timer operation.................................................................................................. 265 9.11.4 watchdog timer operation states...................................................................... 266 section 10 serial communication interface ............................................................... 267 10.1 overview......................................................................................................................... 267 10.2 sci1 ............................................................................................................................ 267 10.2.1 overview............................................................................................................. 267 10.2.2 register descriptions.......................................................................................... 269 10.2.3 operation ............................................................................................................ 274 10.2.4 interrupts............................................................................................................. 277 10.3 sci2 ............................................................................................................................ 278 10.3.1 overview............................................................................................................. 278 10.3.2 register descriptions.......................................................................................... 280 10.3.3 operation ............................................................................................................ 285 10.3.4 interrupts............................................................................................................. 292 section 11 14-bit pwm ................................................................................................... 293 11.1 overview......................................................................................................................... 293 11.1.1 features............................................................................................................... 293 11.1.2 block diagram.................................................................................................... 293 11.1.3 pin configuration................................................................................................ 294 11.1.4 register configuration........................................................................................ 294 11.2 register descriptions...................................................................................................... 295 11.2.1 pwm control register (pwcr) ........................................................................ 295 11.2.2 pwm data registers u and l (pwdru, pwdrl) .......................................... 296 11.3 operation ........................................................................................................................ 297 section 12 a/d converter ................................................................................................ 299 12.1 overview......................................................................................................................... 299 12.1.1 features............................................................................................................... 299 12.1.2 block diagram.................................................................................................... 299 12.1.3 pin configuration................................................................................................ 300 12.1.4 register configuration........................................................................................ 300 12.2 register descriptions...................................................................................................... 301 12.2.1 a/d result register (adrr) ............................................................................. 301 12.2.2 a/d mode register (amr) ................................................................................ 301 12.2.3 a/d start register (adsr) ................................................................................ 303 12.3 operation ........................................................................................................................ 304 12.3.1 a/d conversion operation ................................................................................. 304 12.3.2 start of a/d conversion by external trigger input ........................................... 304 12.4 interrupts......................................................................................................................... 305 12.5 typical use..................................................................................................................... 305 12.6 application notes ........................................................................................................... 308 section 13 d/a converter ................................................................................................ 309 13.1 overview......................................................................................................................... 309 13.1.1 features............................................................................................................... 309 13.1.2 block diagram.................................................................................................... 310 13.1.3 pin configuration................................................................................................ 311 13.1.4 register configuration........................................................................................ 311 13.2 register descriptions...................................................................................................... 312 13.2.1 d/a data registers 3 to 0 (dadr3 to dadr0) ............................................... 312 13.3.2 d/a control register 0 (dacr0) ...................................................................... 312 13.3 operation ........................................................................................................................ 314 13.4 d/a converter operation states..................................................................................... 315 13.5 application notes ........................................................................................................... 315 section 14 electrical characteristics ............................................................................ 317 14.1 absolute maximum ratings ........................................................................................... 317 14.2 electrical characteristics ................................................................................................ 318 14.2.1 power supply voltage and operating range ..................................................... 318 14.2.2 dc characteristics .............................................................................................. 320 14.2.3 ac characteristics .............................................................................................. 326 14.2.4 a/d converter characteristics............................................................................ 329 14.2.5 d/a converter characteristics............................................................................ 330 14.3 operation timing............................................................................................................ 331 14.4 output load circuit........................................................................................................ 335 appendix a cpu instruction set .................................................................................. 337 a.1 instructions ..................................................................................................................... 337 a.2 operation code map....................................................................................................... 345 a.3 number of execution states ........................................................................................... 347 appendix b on-chip registers ..................................................................................... 354 b.1 i/o registers (1) ............................................................................................................. 354 b.2 i/o registers (2) ............................................................................................................. 358 appendix c i/o port block diagrams ......................................................................... 411 c.1 block diagrams of port 1 ............................................................................................... 411 c.2 block diagrams of port 3 ............................................................................................... 418 c.3 block diagram of port 4................................................................................................. 426 c.4 block diagrams of port 5 ............................................................................................... 427 c.5 block diagram of port 6................................................................................................. 431 c.6 block diagrams of port 7 ............................................................................................... 432 c.7 block diagrams of port 8 ............................................................................................... 436 c.8 block diagram of port b ................................................................................................ 444 c.9 block diagram of port c ................................................................................................ 445 appendix d port states in the different processing states ................................... 446 appendix e package dimensions ................................................................................. 447 section 1 overview 1.1 overview the h8/300l series is a series of single-chip microcomputers (mcu: microcomputer unit), built around the high-speed h8/300l cpu and equipped with peripheral system functions on-chip. within the h8/300l series, the h8/3927 series of microcomputers are equipped with d/a converters. other on-chip peripheral functions include 10 timers, a 14-bit pulse width modulator (pwm), two serial communication interface channels, an a/d converter, and a realtime output port. together, these functions make the h8/3927 series ideally suited for embedded applications in advanced control systems. the size of the on-chip rom is 60 kbytes in the h8/3927, 48 kbytes in the h8/3926, 40 kbytes in the h8/3925, and 32 kbytes in the h8/3924. each model has 1 kbyte of on-chip ram. the ztat * versions of the h8/3927 come with user-programmable prom. table 1 summarizes the features of the h8/3927 series. note: * ztat is a trademark of hitachi, ltd. table 1-1 features item description cpu high-speed h8/300l cpu general-register architecture general registers: sixteen 8-bit registers (can be used as eight 16-bit registers) operating speed max. operating speed: 5 mhz add/subtract: 0.4 s (operating at 5 mhz) multiply/divide: 2.8 s (operating at 5 mhz) can run on 32.768 khz subclock instruction set compatible with h8/300 cpu instruction length of 2 bytes or 4 bytes basic arithmetic operations between registers mov instruction for data transfer between memory and registers typical instructions multiply (8 bits 8 bits) divide (16 bits ? 8 bits) bit accumulator register-indirect designation of bit position 1 table 1-1 features (cont) item description interrupts 35 interrupt sources 13 external interrupt sources (nmi, irq 3 to irq 0 , int 7 to int 0 ) 22 internal interrupt sources clock pulse generators two on-chip clock pulse generators system clock pulse generator: 1 to 10 mhz subclock pulse generator: 32.768 khz power-down modes seven power-down modes sleep (high-speed) mode sleep (medium-speed) mode standby mode watch mode subsleep mode subactive mode active (medium-speed) mode memory large on-chip memory h8/3927: 60-kbyte rom; 1-kbyte ram h8/3926: 48-kbyte rom; 1-kbyte ram h8/3925: 40-kbyte rom; 1-kbyte ram h8/3924: 32-kbyte rom; 1-kbyte ram i/o ports 68 pins 56 i/o pins (including 8-pin realtime output port) 12 input pins timers ten on-chip timers timer a: 8-bit timer count-up timer with selection of eight internal clock signals divided from the system clock (? * and four clock signals divided from the watch clock ( w ) * timer b1: 8-bit timer count-up timer with selection of seven internal clock signals or event input from external pin auto-reloading note: * ?and w are defined in section 4, clock pulse generators. 2 table 1-1 features (cont) item description timers timer b2: 8-bit timer count-up timer with selection of seven internal clock signals auto-reloading timer b3: 8-bit timer count-up timer with selection of seven internal clock signals auto-reloading timer c: 8-bit timer count-up/count-down timer with selection of seven internal clock signals or event input from external pin auto-reloading timer e: 8-bit timer count-up timer with selection of eight internal clock signals square-wave output with 50% duty cycle timer v: 8-bit timer count-up timer with selection of six internal clock signals or event input from external pin compare-match waveform output externally triggerable timer x: 16-bit timer count-up timer with selection of three internal clock signals or event input from external pin output compare (2 output pins) input capture (4 input pins) timer y: 16-bit timer count-up timer with selection of seven internal clock signals or event input from external pin auto-reloading watchdog timer reset signal generated by 8-bit counter overflow 3 table 1-1 features (cont) item specification serial communication two channels on chip interface sci1: synchronous serial interface choice of 8-bit or 16-bit data transfer sci2: 8-bit synchronous serial interface automatic transfer of 32-byte data segments 14-bit pwm pulse-division pwm output for reduced ripple can be used as a 14-bit d/a converter by connecting to an external low-pass filter. a/d converter successive approximations using a resistance ladder resolution: 8 bits conversion time: 31/?or 62/? per channel d/a converter 8-bit r-2r-type d/a converter 4 analog output channels product lineup product code mask rom ztat version version package rom/ram size HD6433927f hd6473927f 80-pin qfp rom: 60 kbytes (fp-80b) ram: 1 kbyte hd6433926f rom: 48 kbytes ram: 1 kbyte hd6433925f rom: 40 kbytes ram: 1 kbyte hd6433924f rom: 32 kbytes ram: 1 kbyte HD6433927x hd6473927x 80-pin tqfp rom: 60 kbytes (tfp-80f) ram: 1 kbyte hd6433926x rom: 48 kbytes ram: 1 kbyte hd6433925x rom: 40 kbytes ram: 1 kbyte hd6433924x rom: 32 kbytes ram: 1 kbyte 4 1.2 internal block diagram figure 1-1 shows a block diagram of the h8/3927 series. figure 1-1 block diagram port 8 p8 7 p8 6 /ftid p8 5 /ftic p8 4 /ftib p8 3 /ftia p8 2 /ftob p8 1 /ftoa p8 0 /ftci rom port 7 p7 7 p7 6 /tmov p7 5 /tmciv p7 4 /tmriv p7 3 p7 2 p7 1 p7 0 port 6 p6 7 /rp 7 p6 6 /rp 6 p6 5 /rp 5 p6 4 /rp 4 p6 3 /rp 3 p6 2 /rp 2 p6 1 /rp 1 p6 0 /rp 0 p5 7 /int 7 /tmiy p5 6 /int 6 /tmib p5 5 /int 5 /adtrg p5 4 /int 4 p5 3 /int 3 p5 2 /int 2 p5 1 /int 1 p5 0 /int 0 port 1 p1 0 /tmow p1 1 /tmoe p1 2 /ud p1 3 /tmic p1 4 /pwm p1 5 /irq 1 p1 6 /irq 2 p1 7 /irq 3 /trgv port 3 p3 0 /sck 1 p3 1 /si 1 p3 2 /so 1 p3 3 /sck 2 p3 4 /si 2 p3 5 /so 2 p3 6 /strb p3 7 /cs p4 0 p4 1 p4 2 p4 3 p4 4 p4 5 p4 6 p4 7 port 4 pb 0 /an 0 pb 1 /an 1 pb 2 /an 2 pb 3 /an 3 pb 4 /an 4 pb 5 /an 5 pb 6 /an 6 pb 7 /an 7 pc 0 /da 0 pc 1 /da 1 pc 2 /da 2 pc 3 /da 3 v ss v cc res nmi irq 0 test osc 1 osc 2 x 1 x 2 cpu h8/300l data bus (lower) system clock generator subclock generator ram (1 kbyte) timer a sci1 timer b1 timer b2 timer b3 timer c timer e watchdog timer a/d converter d/a converter sci2 timer x timer y timer v 14-bit pwm av cc av ss port 5 port b port c data bus (upper) address bus 5 1.3 pin arrangement and functions 1.3.1 pin arrangement the h8/3927 series pin arrangement is shown in figures 1-2 and 1-3. figure 1-2 pin arrangement (tfp-80f: top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 64 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p3 0 /sck 1 p3 1 /si 1 p3 2 /so 1 p3 3 /sck 2 p3 4 /si 2 p3 5 /so 2 p3 6 /strb p3 7 /cs p8 7 p8 6 /ftid p8 5 /ftic p8 4 /ftib p8 3 /ftia p8 2 /ftob p8 1 /ftoa p8 0 /ftci p7 7 p7 6 /tmov p7 5 /tmciv p7 4 /tmriv pb 1 /an 1 pb 0 /an 0 av ss test x 2 x 1 v ss osc 1 osc 2 res nmi p4 0 p4 1 p4 2 p4 3 p4 4 p4 5 p4 6 p4 7 irq 0 p5 0 /int 0 p5 1 /int 1 p5 2 /int 2 p5 3 /int 3 p5 4 /int 4 p5 5 /int 5 /adtrg p5 6 /int 6 /tmib p5 7 /int 7 /tmiy p6 0 /rp 0 p6 1 /rp 1 p6 2 /rp 2 p6 3 /rp 3 p6 4 /rp 4 p6 5 /rp 5 p6 6 /rp 6 p6 7 /rp 7 p7 0 p7 1 p7 2 p7 3 pb 2 /an 2 pb 3 /an 3 pb 4 /an 4 pb 5 /an 5 pb 6 /an 6 pb 7 /an 7 pc 0 /da 0 pc 1 /da 1 pc 2 /da 2 pc 3 /da 3 av cc p1 7 /irq 3 /trgv p1 6 /irq 2 p1 5 /irq 1 p1 4 /pwm p1 3 /tmic p1 2 /ud p1 1 /tmoe p1 0 /tmow v cc 6 figure 1-3 pin arrangement (fp-80b: top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 p1 0 /tmow v cc p3 0 /sck 1 p3 1 /si 1 p3 2 /so 1 p3 3 /sck 2 p3 4 /si 2 p3 5 /so 2 p3 6 /strb p3 7 / cs p8 7 p8 6 /ftid p8 5 /ftic p8 4 /ftib p8 3 /ftia p8 2 /ftob p8 1 /ftoa p8 0 /ftci p7 7 p7 6 /tmov p7 5 /tmciv p7 4 /tmriv p7 3 p7 2 pb 3 /an 3 pb 2 /an 2 pb 1 /an 1 pb 0 /an 0 av ss test x 2 x 1 v ss osc 1 osc 2 res nmi p4 0 p4 1 p4 2 p4 3 p4 4 p4 5 p4 6 p4 7 irq 0 p5 0 /int 0 p5 1 /int 1 pb 4 /an 4 pb 5 /an 5 pb 6 /an 6 pb 7 /an 7 pc 0 /da 0 pc 1 /da 1 pc 2 /da 2 pc 3 /da 3 av cc p1 7 /irq 3 /trgv p1 6 /irq 2 p1 5 /irq 1 p1 4 /pwm p1 3 /tmic p1 2 /ud p1 1 /tmoe p5 2 /int 2 p5 3 /int 3 p5 4 /int 4 p5 5 /int 5 /adtrg p5 6 /int 6 /tmib p5 7 /int 7 /tmiy p6 0 /rp 0 p6 1 /rp 1 p6 2 /rp 2 p6 3 /rp 3 p6 4 /rp 4 p6 5 /rp 5 p6 6 /rp 6 p6 7 /rp 7 p7 0 p7 1 7 1.3.2 pin functions table 1-2 outlines the pin functions of the h8/3927 series. table 1-2 pin functions pin no. type symbol tfp-80f fp-80b i/o name and functions power v cc 61 63 input power supply: all v cc pins should be source pins connected to the system power supply (+5 v) v ss 7 9 input ground: all v ss pins should be connected to the system power supply (0 v) av cc 70 72 input analog power supply: this is the power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply (+5 v). av ss 3 5 input analog ground: this is the a/d converter ground pin. it should be connected to the system power supply (0 v). clock pins osc 1 8 10 input system clock: these pins connect to a crystal or ceramic oscillator, or can be osc 2 9 11 output used to input an external clock. see section 4, clock pulse generators, for a typical connection diagram. x 1 6 8 input subclock: these pins connect to a 32.768-khz crystal oscillator. x 2 5 7 output see section 4, clock pulse generators, for a typical connection diagram. system res 10 12 input reset: when this pin is driven low, control the chip is reset test 4 6 input test: this is a test pin, not for use in application systems. it should be connected to v ss . 8 table 1-2 pin functions (cont) pin no. type symbol tfp-80f fp-80b i/o name and functions interrupt nmi 11 13 input nonmaskable interrupt: this is an pins input pin for an edge-sensitive nonmaskable interrupt, with a selection of rising or falling edge. irq 0 20 22 input irq interrupt request 0 to 3: these irq 1 67 69 are input pins for edge-sensitive external irq 2 68 70 interrupts, with a selection of rising or irq 3 69 71 falling edge. int 7 to 28 to 30 to input int interrupt request 0 to 7: these int 0 21 23 are input pins for edge-sensitive external interrupts, with a selection of rising or falling edge. timer pins tmow 62 64 output clock output: this is an output pin for waveforms generated by the timer a output circuit tmib 27 29 input timer b1 event counter input: this is an event input pin for input to the timer b1 counter tmic 65 67 input timer c event counter input: this is an event input pin for input to the timer c counter ud 64 66 input timer c up/down select: this pin selects whether timer c counts up or down. high input selects up-counting. low input selects down-counting. tmoe 63 65 output timer e output: this is an output pin for a square wave generated by counter overflow in timer e tmov 43 45 output timer v output: this is an output pin for waveforms generated by the timer v output compare function tmciv 42 44 input timer v event input: this is an event input pin for input to the timer v counter tmriv 41 43 input timer v counter reset: this is a counter reset input pin for timer v 9 table 1-2 pin functions (cont) pin no. type symbol tfp-80f fp-80b i/o name and functions timer pins trgv 69 71 input timer v counter trigger input: this is a trigger input pin for the timer v counter and realtime output port. ftci 45 47 input timer x clock input: this is an external clock input pin for input to the timer x counter ftoa 46 48 output timer x output compare a output: this is an output pin for timer x output compare a ftob 47 49 output timer x output compare b output: this is an output pin for timer x output compare b ftia 48 50 input timer x input capture a input: this is an input pin for timer x input capture a ftib 49 51 input timer x input capture b input: this is an input pin for timer x input capture b ftic 50 52 input timer x input capture c input: this is an input pin for timer x input capture c ftid 51 53 input timer x input capture d input: this is an input pin for timer x input capture d tmiy 28 30 input timer y clock input: this is an external clock input pin for input to the timer y counter 14-bit pwm 66 68 output 14-bit pwm output: this is an output pwm pin pin for waveforms generated by the 14-bit pwm i/o ports pb 7 to 75 to 80, 77 to 80, input port b: this is an 8-bit input port pb 0 1 to 2 1 to 4 pc 3 to 71 to 73 to input port c: this is a 4-bit input port pc 0 74 76 p1 7 to 69 to 71 to i/o port 1: this is an 8-bit i/o port. input p1 0 62 64 or output can be designated for each bit by means of port control register 1 (pcr1). p3 7 to 53 to 55 to i/o port 3: this is an 8-bit i/o port. input p3 0 60 62 or output can be designated for each bit by means of port control register 3 (pcr3). 10 11 table 1-2 pin functions (cont) pin no. type symbol tfp-80f fp-80b i/o name and functions i/o ports p4 7 to 19 to 21 to i/o port 4: this is an 8-bit i/o port. input or p4 0 12 14 output can be designated for each pin by means of port control register 4 (pcr4). p5 7 to 28 to 30 to i/o port 5: this is an 8-bit i/o port. input p5 0 21 23 or output can be designated for each bit by means of port control register 5 (pcr5). p6 7 to 36 to 38 to i/o port 6: this is an 8-bit i/o port. input p6 0 29 31 or output can be designated for each bit by means of port control register 6 (pcr6). rp 7 to 36 to 38 to output port 6: this is an 8-bit realtime output rp 0 29 31 port p7 7 to 44 to 46 to i/o port 7: this is an 8-bit i/o port. input p7 0 37 39 or output can be designated for each bit by means of port control register 7 (pcr7). p8 7 to 52 to 54 to i/o port 8: this is an 8-bit i/o port. input p8 0 45 47 or output can be designated for each bit by means of port control register 8 (pcr8). serial si 1 59 61 input sci1 receive data input: communi- this is the sci1 data input pin cation so 1 58 60 output sci1 send data output: interface this is the sci1 data output pin (sci) sck 1 60 62 i/o sci1 clock i/o : this is the sci1 clock i/o pin si 2 56 58 input sci2 receive data input: this is the sci2 data input pin so 2 55 57 output sci2 send data output: this is the sci2 data output pin sck 2 57 59 i/o sci2 clock i/o : this is the sci2 clock i/o pin cs 53 55 input sci2 chip select input: this pin controls the start of sci2 transfers strb 54 56 output sci2 strobe output: this pin outputs a strobe pulse each time a byte of data is transferred table 1-2 pin functions (cont) pin no. type symbol tfp-80f fp-80b i/o name and functions a/d an 7 to 79 to 80, 77 to 80, input analog input channels 7 to 0: converter an 0 1 to 2 1 to 4 these are analog data input channels to the a/d converter adtrg 26 28 input a/d converter trigger input: this is the external trigger input pin to the a/d converter d/a da 3 to 71 to 73 to output analog output channels 3 to 0: these converter da 0 74 76 are analog data output channels from the d/a converter 12 section 2 cpu 2.1 overview the h8/300l cpu has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. its concise instruction set is designed for high-speed operation. 2.1.1 features features of the h8/300l cpu are listed below. general-register architecture sixteen 8-bit general registers, also usable as eight 16-bit general registers instruction set with 55 basic instructions, including: multiply and divide instructions powerful bit-manipulation instructions eight addressing modes register direct register indirect register indirect with displacement register indirect with post-increment or pre-decrement absolute address immediate program-counter relative memory indirect 64-kbyte address space high-speed operation all frequently used instructions are executed in two to four states high-speed arithmetic and logic operations 8- or 16-bit register-register add or subtract: 0.4 s* 8 8-bit multiply: 2.8 s* 16 8-bit divide: 2.8 s* low-power operation modes sleep instruction for transfer to low-power operation note: * these values are at ?= 5 mhz. 13 2.1.2 address space the h8/300l cpu supports an address space of up to 64 kbytes for storing program code and data. see 2.8, memory map, for details of the memory map. 2.1.3 register configuration figure 2-1 shows the register structure of the h8/300l cpu. there are two groups of registers: the general registers and control registers. figure 2-1 cpu registers 7 0 7 0 15 0 pc r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l (sp) sp: stack pointer pc: program counter ccr: condition code register carry flag overflow flag zero flag negative flag half-carry flag interrupt mask bit user bit user bit ccr i u h u n z v c general registers (rn) control registers (cr) 7 5 3 2 1 0 6 4 14 2.2 register descriptions 2.2.1 general registers all the general registers can be used as both data registers and address registers. when used as data registers, they can be accessed as 16-bit registers (r0 to r7), or the high bytes (r0h to r7h) and low bytes (r0l to r7l) can be accessed separately as 8-bit registers. when used as address registers, the general registers are accessed as 16-bit registers (r0 to r7). r7 also functions as the stack pointer (sp), used implicitly by hardware in exception processing and subroutine calls. when it functions as the stack pointer, as indicated in figure 2-2, sp (r7) points to the top of the stack. figure 2-2 stack pointer 2.2.2 control registers the cpu control registers include a 16-bit program counter (pc) and an 8-bit condition code register (ccr). program counter (pc): this 16-bit register indicates the address of the next instruction the cpu will execute. all instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the pc is ignored (always regarded as 0). lower address side [h'0000] upper address side [h'ffff] unused area stack area sp (r7) 15 condition code register (ccr): this 8-bit register contains internal status information, including the interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. these bits can be read and written by software (using the ldc, stc, andc, orc, and xorc instructions). the n, z, v, and c flags are used as branching conditions for conditional branching (bcc) instructions. bit 7?nterrupt mask bit (i): when this bit is set to 1, interrupts are masked. this bit is set to 1 automatically at the start of exception handling. the interrupt mask bit may be read and written by software. for further details, see section 3.3, interrupts. bit 6?ser bit (u): can be used freely by the user. bit 5?alf-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. the h flag is used implicitly by the daa and das instructions. when the add.w, sub.w, or cmp.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. bit 4?ser bit (u): can be used freely by the user. bit 3?egative flag (n): indicates the most significant bit (sign bit) of the result of an instruction. bit 2?ero flag (z): set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. bit 1?verflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0?arry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: add instructions, to indicate a carry subtract instructions, to indicate a borrow shift and rotate instructions, to store the value shifted out of the end bit the carry flag is also used as a bit accumulator by bit manipulation instructions. some instructions leave some or all of the flag bits unchanged. refer to the h8/300l series programming manual for the action of each instruction on the flag bits. 16 2.2.3 initial register values when the cpu is reset, the program counter (pc) is initialized to the value stored at address h'0000 in the vector table, and the i bit in the ccr is set to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (r7) is not initialized. the stack pointer should be initialized by software, by the first instruction executed after a reset. 2.3 data formats the h8/300l cpu can process 1-bit data, 4-bit (bcd) data, 8-bit (byte) data, and 16-bit (word) data. bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). all arithmetic and logic instructions except adds and subs can operate on byte data. the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions operate on word data. the daa and das instructions perform decimal arithmetic adjustments on byte data in packed bcd form. each nibble of the byte is treated as a decimal digit. 17 2.3.1 data formats in general registers data of all the sizes above can be stored in general registers as shown in figure 2-3. figure 2-3 register data formats 7 6 5 4 3 2 1 0 don? care data type register no. data format 7 0 1-bit data rnh 7 6 5 4 3 2 1 0 don? care 7 0 1-bit data rnl msb lsb don? care 7 0 byte data rnh byte data rnl word data rn 4-bit bcd data rnh 4-bit bcd data rnl notation: rnh: rnl: msb: lsb: upper byte of general register lower byte of general register most significant bit least significant bit msb lsb don? care 7 0 msb lsb 15 0 upper digit lower digit don? care 7 0 3 4 don? care upper digit lower digit 7 0 3 4 h8/3834 '92 fig. 2-3 18 2.3.2 memory data formats figure 2-4 indicates the data formats in memory. for access by the h8/300l cpu, word data stored in memory must always begin at an even address. in word access the least significant bit of the address is regarded as 0. if an odd address is specified, the access is performed at the preceding even address. this rule affects the mov.w instruction, and also applies to instruction fetching. figure 2-4 memory data formats when the stack is accessed using r7 as an address register, word access should always be performed. when the ccr is pushed on the stack, two identical copies of the ccr are pushed to make a complete word. when they are restored, the lower byte is ignored. data format 7 6 5 4 3 2 1 0 address data type 7 0 address n msb lsb msb lsb upper 8 bits lower 8 bits msb lsb ccr ccr * msb lsb msb lsb address n even address odd address even address odd address even address odd address 1-bit data byte data word data byte data (ccr) on stack word data on stack ccr: condition code register h8/3834 '92 fig. 2-4 note: ignored on return * 19 2.4 addressing modes 2.4.1 addressing modes the h8/300l cpu supports the eight addressing modes listed in table 2-1. each instruction uses a subset of these addressing modes. table 2-1 addressing modes no. address modes symbol 1 register direct rn 2 register indirect @rn 3 register indirect with displacement @(d:16, rn) 4 register indirect with post-increment @rn+ register indirect with pre-decrement @?n 5 absolute address @aa:8 or @aa:16 6 immediate #xx:8 or #xx:16 7 program-counter relative @(d:8, pc) 8 memory indirect @@aa:8 1. register direct?n: the register field of the instruction specifies an 8- or 16-bit general register containing the operand. only the mov.w, add.w, sub.w, cmp.w, adds, subs, mulxu (8 bits 8 bits), and divxu (16 bits 8 bits) instructions have 16-bit operands. 2. register indirect?rn: the register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. 3. register indirect with displacement?(d:16, rn): the instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory. this mode is used only in mov instructions. for the mov.w instruction, the resulting address must be even. 20 4. register indirect with post-increment or pre-decrement?rn+ or @?n: register indirect with post-increment?rn+ the @rn+ mode is used with mov instructions that load registers from memory. the register field of the instruction specifies a 16-bit general register containing the address of the operand. after the operand is accessed, the register is incremented by 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the 16-bit general register must be even. register indirect with pre-decrement??n the @?n mode is used with mov instructions that store register contents to memory. the register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. the register retains the decremented value. the size of the decrement is 1 for mov.b or 2 for mov.w. for mov.w, the original contents of the register must be even. 5. absolute address?aa:8 or @aa:16: the instruction specifies the absolute address of the operand in memory. the absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). the mov.b and bit manipulation instructions can use 8-bit absolute addresses. the mov.b, mov.w, jmp, and jsr instructions can use 16-bit absolute addresses. for an 8-bit absolute address, the upper 8 bits are assumed to be 1 (h'ff). the address range is h'ff00 to h'ffff (65280 to 65535). 6. immediate?xx:8 or #xx:16: the instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. only mov.w instructions can contain 16-bit immediate values. the adds and subs instructions implicitly contain the value 1 or 2 as immediate data. some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. program-counter relative?(d:8, pc): this mode is used in the bcc and bsr instructions. an 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. the possible branching range is ?26 to +128 bytes (?3 to +64 words) from the current address. the displacement should be an even number. 21 8. memory indirect?@aa:8: this mode can be used by the jmp and jsr instructions. the second byte of the instruction code specifies an 8-bit absolute address. the word located at this address contains the branch destination address. the upper 8 bits of the absolute address are assumed to be 0 (h'00), so the address range is from h'0000 to h'00ff (0 to 255). note that with the h8/300l series, the lower end of the address area is also used as a vector area. see 3.3, interrupts, for details on the vector area. if an odd address is specified as a branch destination or as the operand address of a mov.w instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. see 2.3.2, memory data formats, for further information. 2.4.2 effective address calculation table 2-2 shows how effective addresses are calculated in each of the addressing modes. arithmetic and logic instructions use register direct addressing (1). the add.b, addx, subx, cmp.b, and, or, and xor instructions can also use immediate addressing (6). data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). bit manipulation instructions use register direct (1), register indirect (2), or absolute addressing (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte. the bset, bclr, bnot, and btst instructions can also use register direct addressing (1) to specify the bit position. 22 table 2-2 effective address calculation addressing mode and instruction format op rm 7 6 3 4 0 15 no. effective address calculation method effective address (ea) 1 register direct, rn operand is contents of registers indicated by rm/rn register indirect, @rn contents (16 bits) of register indicated by rm 0 15 register indirect with displacement, @(d:16, rn) op rm rn 8 7 3 4 0 15 op rm 7 6 3 4 0 15 disp op rm 7 6 3 4 0 15 register indirect with post-increment, @rn+ op rm 7 6 3 4 0 15 register indirect with pre-decrement, @ern 2 3 4 incremented or decremented by 1 if operand is byte size, and by 2 if word size 0 15 disp 0 15 0 15 0 15 1 or 2 0 15 0 15 1 or 2 0 15 rm 3 0 rn 3 0 contents (16 bits) of register indicated by rm contents (16 bits) of register indicated by rm contents (16 bits) of register indicated by rm 23 table 2-2 effective address calculation (cont) addressing mode and instruction format no. effective address calculation method effective address (ea) 5 absolute address @aa:8 operand is 1- or 2-byte immediate data @aa:16 op 8 7 0 15 op 0 15 imm op disp 7 0 15 program-counter relative @(d:8, pc) 6 7 0 15 pc contents 0 15 0 15 abs h'ff 8 7 0 15 0 15 abs op #xx:16 op 8 7 0 15 imm immediate #xx:8 8 sign extension disp 24 table 2-2 effective address calculation (cont) addressing mode and instruction format no. effective address calculation method effective address (ea) 8 memory indirect, @@aa:8 op 8 7 0 15 memory contents (16 bits) 0 15 abs h'00 8 7 0 15 notation: rm, rn: op: disp: imm: abs: register field operation field displacement immediate data absolute address abs 25 2.5 instruction set the h8/300l series can use a total of 55 instructions, which are grouped by function in table 2-3. table 2-3 instruction set function instructions number data transfer mov, push * 1 , pop * 1 1 arithmetic operations add, sub, addx, subx, inc, dec, adds, 14 subs, daa, das, mulxu, divxu, cmp, neg logic operations and, or, xor, not 4 shift shal, shar, shll, shlr, rotl, rotr, 8 rotxl, rotxr bit manipulation bset, bclr, bnot, btst, band, biand, bor, 14 bior, bxor, bixor, bld, bild, bst, bist branch bcc *2 , jmp, bsr, jsr, rts 5 system control rte, sleep, ldc, stc, andc, orc, xorc, nop 8 block data transfer eepmov 1 total: 55 notes: 1. push rn is equivalent to mov.w rn, @?p. pop rn is equivalent to mov.w @sp+, rn. 2. bcc is a conditional branch instruction in which cc represents a condition code. the following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. the notation used is defined next. 26 notation rd general register (destination) rs general register (source) rn general register (ead), 2.5.1 data transfer instructions table 2-4 describes the data transfer instructions. figure 2-5 shows their object code formats. table 2-4 data transfer instructions instruction size * function mov b/w (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. the rn, @rn, @(d:16, rn), @aa:16, #xx:16, @?n, and @rn+ addressing modes are available for byte or word data. the @aa:8 addressing mode is available for byte data only. the @?7 and @r7+ modes require word operands. do not specify byte size for these two modes. pop w @sp+ rn pops a 16-bit general register from the stack. equivalent to mov.w @sp+, rn. push w rn @?p pushes a 16-bit general register onto the stack. equivalent to mov.w rn, @?p. notes: * size: operand size b: byte w: word certain precautions are required in data access. see 2.9.1, notes on data access, for details. 28 figure 2-5 data transfer instruction codes 15 0 8 7 op rm rn mov rm ? rn 15 0 8 7 op rm rn @rm ?? rn 15 0 8 7 op rm rn @(d:16, rm) ?? rn disp 15 0 8 7 op rm rn @rm+ ? rn, or rn ? @erm 15 0 8 7 op rn abs @aa:8 ?? rn 15 0 8 7 op rn @aa:16 ?? rn abs 15 0 8 7 op rn imm #xx:8 ? rn 15 0 8 7 op rn #xx:16 ? rn imm 15 0 8 7 op rn push, pop notation: op: rm, rn: disp: abs: imm: operation field register field displacement absolute address immediate data h8/3834 '92 fig. 2-5 @sp+ rn, or rn @esp ? ? 1 1 1 29 2.5.2 arithmetic operations table 2-5 describes the arithmetic instructions. table 2-5 arithmetic instructions instruction size * function add b/w rd rs rd, rd + #imm rd sub performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. immediate data cannot be subtracted from data in a general register. word data can be added or subtracted only when both words are in general registers. addx b rd rs c rd, rd #imm c rd subx performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. inc b rd 1 rd dec increments or decrements a general register adds w rd 1 rd, rd 2 rd subs adds or subtracts 1 or 2 to or from a general register daa b rd decimal adjust rd das decimal-adjusts (adjusts to packed bcd) an addition or subtraction result in a general register by referring to the ccr mulxu b rd rs rd performs 8-bit 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result divxu b rd rs rd performs 16-bit 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder cmp b/w rd ?rs, rd ?#imm compares data in a general register with data in another general register or with immediate data, and indicates the result in the ccr. word data can be compared only between two general registers. neg b 0 ?rd rd obtains the two? complement (arithmetic complement) of data in a general register notes: * size: operand size b: byte w: word 30 2.5.3 logic operations table 2-6 describes the four instructions that perform logic operations. table 2-6 logic operation instructions instruction size * function and b rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data or b rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data xor b rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data not b ~ rd rd obtains the one? complement (logical complement) of general register contents notes: * size: operand size b: byte 2.5.4 shift operations table 2-7 describes the eight shift instructions. table 2-7 shift instructions instruction size * function shal b rd shift rd shar performs an arithmetic shift operation on general register contents shll b rd shift rd shlr performs a logical shift operation on general register contents rotl b rd rotate rd rotr rotates general register contents rotxl b rd rotate through carry rd rotxr rotates general register contents through the c (carry) bit notes: * size: operand size b: byte 31 figure 2-6 shows the instruction code format of arithmetic, logic, and shift instructions. figure 2-6 arithmetic, logic, and shift instruction codes 15 0 8 7 op rm rn add, sub, cmp, addx, subx (rm) notation: op: rm, rn: imm: operation field register field immediate data 15 0 8 7 op rn adds, subs, inc, dec, daa, das, neg, not 15 0 8 7 op rn mulxu, divxu rm 15 0 8 7 rn imm add, addx, subx, cmp (#xx:8) op 15 0 8 7 op rn and, or, xor (rm) rm 15 0 8 7 rn imm and, or, xor (#xx:8) op 15 0 8 7 rn shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr op h8/3834 '92 fig. 2-6 32 2.5.5 bit manipulations table 2-8 describes the bit-manipulation instructions. figure 2-7 shows their object code formats. table 2-8 bit-manipulation instructions instruction size * function bset b 1 ( table 2-8 bit-manipulation instructions (cont) instruction size * function bxor b c ( figure 2-7 bit manipulation instruction codes 15 0 8 7 op imm rn operand: bit no.: notation: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 8 7 op rn bset, bclr, bnot, btst register direct (rn) immediate (#xx:3) operand: bit no.: register direct (rn) register direct (rm) rm 15 0 8 7 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm 15 0 8 7 op 0 operand: bit no.: register indirect (@rn) register direct (rm) rn 0 0 0 0 0 0 0 rm op 15 0 8 7 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0 0 0 0 imm op op 15 0 8 7 op operand: bit no.: absolute (@aa:8) register direct (rm) abs 0 0 0 0 rm op 15 0 8 7 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) band, bor, bxor, bld, bst 15 0 8 7 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 8 7 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0 0 0 0 imm op h8/3834 '92 fig. 2-7 35 figure 2-7 bit manipulation instruction codes (cont) notation: op: rm, rn: abs: imm: operation field register field absolute address immediate data 15 0 8 7 op imm rn operand: bit no.: register direct (rn) immediate (#xx:3) biand, bior, bixor, bild, bist 15 0 8 7 op 0 operand: bit no.: register indirect (@rn) immediate (#xx:3) rn 0 0 0 0 0 0 0 imm op 15 0 8 7 op operand: bit no.: absolute (@aa:8) immediate (#xx:3) abs 0 0 0 0 imm op h8/3834 '92 fig. 2-7 (cont) 36 2.5.6 branching instructions table 2-9 describes the branching instructions. figure 2-8 shows their object code formats. table 2-9 branching instructions instruction size function bcc branches to the designated address if condition cc is true. the branching conditions are given below. mnemonic description condition bra (bt) always (true) always brn (bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc (bhs) carry clear (high or same) c = 0 bcs (blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp branches unconditionally to a specified address bsr branches to a subroutine at a specified address jsr branches to a subroutine at a specified address rts returns from a subroutine 37 figure 2-8 branching instruction codes notation: op: cc: rm: disp: abs: operation field condition field register field displacement absolute address 15 0 8 7 op cc disp bcc 15 0 8 7 op rm 0 jmp (@rm) 0 0 0 15 0 8 7 op jmp (@aa:16) abs 15 0 8 7 op abs jmp (@@aa:8) 15 0 8 7 op disp bsr 15 0 8 7 op rm 0 jsr (@rm) 0 0 0 15 0 8 7 op jsr (@aa:16) abs 15 0 8 7 op abs jsr (@@aa:8) 15 0 8 7 op rts h8/3834 '92 fig. 2-8 38 2.5.7 system control instructions table 2-10 describes the system control instructions. figure 2-9 shows their object code formats. table 2-10 system control instructions instruction size * function rte returns from an exception-handling routine sleep causes a transition from active mode to a power-down mode. see section 5, power-down modes, for details. ldc b rs ccr, #imm ccr moves immediate data or general register contents to the condition code register stc b ccr rd copies the condition code register to a specified general register andc b ccr #imm ccr logically ands the condition code register with immediate data orc b ccr #imm ccr logically ors the condition code register with immediate data xorc b ccr #imm ccr logically exclusive-ors the condition code register with immediate data nop pc + 2 pc only increments the program counter notes: * size: operand size b: byte 39 figure 2-9 system control instruction codes 2.5.8 block data transfer instruction table 2-11 describes the block data transfer instruction. figure 2-10 shows its object code format. table 2-11 block data transfer instruction instruction size function eepmov if r4l 0 then repeat @r5+ @r6+ r4l ?1 r4l until r4l = 0 else next; moves a data block according to parameters set in general registers r4l, r5, and r6. r4l: size of block (bytes) r5: starting source address r6: starting destination address execution of the next instruction starts as soon as the block transfer is completed. certain precautions are required in using the eepmov instruction. see 2.9.3, notes on use of the eepmov instruction, for details. notation: op: rn: imm: operation field register field immediate data 15 0 8 7 op rte, sleep, nop 15 0 8 7 op rn ldc, stc (rn) 15 0 8 7 op imm andc, orc, xorc, ldc (#xx:8) h8/3834 '92 fig. 2-9 40 figure 2-10 block data transfer instruction code notation: op: operation field 15 0 8 7 op op h8/3834 '92 fig. 2-10 41 2.6 basic operational timing cpu operation is synchronized by a system clock (? or a subclock ( sub ). for details on these clock signals see section 4, clock pulse generators. the period from a rising edge of ?or sub to the next rising edge is called one state. a bus cycle consists of two states or three states. the cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 access to on-chip memory (ram, rom) access to on-chip memory takes place in two states. the data bus width is 16 bits, allowing access in byte or word size. figure 2-11 shows the on-chip memory access cycle. figure 2-11 on-chip memory access cycle t 1 state bus cycle t 2 state internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) h8/3834 '92 fig. 2-11&2-12 sub ?or 42 2.6.2 access to on-chip peripheral modules on-chip peripheral modules are accessed in two states or three states. the data bus width is 8 bits, so access is by byte size only. this means that for accessing word data, two instructions must be used. figures 2-12 and 2-13 show the on-chip peripheral module access cycle. two-state access to on-chip peripheral modules figure 2-12 on-chip peripheral module access cycle (2-state access) t 1 state bus cycle t 2 state ?or internal address bus internal read signal internal data bus (read access) internal write signal read data address write data internal data bus (write access) h8/3834 '92 fig. 2-12 sub 43 three-state access to on-chip peripheral modules figure 2-13 on-chip peripheral module access cycle (3-state access) t 1 state bus cycle internal address bus internal read signal internal data bus (read access) internal write signal read data address internal data bus (write access) h8/3834 '92 fig. 2-13 t 2 state t 3 state write data sub ?or 44 2.7 cpu states 2.7.1 overview there are four cpu states: the reset state, program execution state, program halt state, and exception-handling state. the program execution state includes active (high-speed or medium- speed) mode and subactive mode. in the program halt state there are a sleep (high-speed or medium-speed) mode, standby mode, watch mode, and sub-sleep mode. these states are shown in figure 2-14. figure 2-15 shows the state transitions. figure 2-14 cpu operation states cpu state reset state program execution state program halt state exception- handling state active (high speed) mode active (medium speed) mode subactive mode sleep (high-speed) mode standby mode watch mode subsleep mode low-power modes the cpu executes successive program instructions at high speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the system clock the cpu executes successive program instructions at reduced speed, synchronized by the subclock a state in which some or all of the chip functions are stopped to conserve power a transient state in which the cpu changes the processing flow due to a reset or an interrupt the cpu is initialized note: see section 5, power-down modes, for details on the modes and their transitions. sleep (medium-speed) mode 45 figure 2-15 state transitions 2.7.2 program execution state in the program execution state the cpu executes program instructions in sequence. there are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. see section 5, power-down modes for details on these modes. 2.7.3 program halt state in the program halt state there are four modes: sleep mode, standby mode, watch mode, and subsleep mode. see section 5, power-down modes for details on these modes. 2.7.4 exception-handling state the exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the cpu changes its normal processing flow. in exception handling caused by an interrupt, sp (r7) is referenced and the pc and ccr values are saved on the stack. for details on interrupt handling, see section 3.3, interrupts. h037 '92 h8/343 u.m. fig. 2-15 reset state program halt state exception-handling state program execution state reset cleared sleep instruction executed reset occurs interrupt source reset occurs exception- handling request exception- handling complete reset occurs 46 2.8 memory map 2.8.1 memory map figure 2-16 shows a memory map of the h8/3927 series. figure 2-16 h8/3927 series memory map h'0000 h'002f h'0030 h'7fff h'9fff h'bfff h'edff h'f740 h'f77f h'fb80 h'ff7f h'ff80 h'ff9f h'ffa0 h'ffff interrupt vectors on-chip rom reserved internal i/o registers (64 bytes) reserved on-chip ram 32-byte serial data buffer internal i/o registers (96 bytes) 32 kbytes 40 kbytes 48 kbytes 60 kbytes 1024 bytes h8/3924 h8/3925 h8/3926 h8/3927 47 2.9 application notes 2.9.1 notes on data access 1. the address space of the h8/300l cpu includes empty areas in addition to the ram, registers, and rom areas available to the user. if these empty areas are mistakenly accessed by an application program, the following results will occur. data transfer from cpu to empty area: the transferred data will be lost. this action may also cause the cpu to misoperate. data transfer from empty area to cpu: unpredictable data is transferred. 2. internal data transfer to or from on-chip modules other than the rom and ram areas makes use of an 8-bit data width. if word access is attempted to these areas, the following results will occur. word access from cpu to i/o register area: upper byte: will be written to i/o register. lower byte: transferred data will be lost. word access from i/o register to cpu: upper byte: will be written to upper part of cpu register. lower byte: unpredictable data will be written to lower part of cpu register. byte size instructions should therefore be used when transferring data to or from i/o registers other than the on-chip rom and ram areas. figure 2-17 shows the data size and number of states in which on-chip peripheral modules can be accessed. 48 figure 2-17 data size and number of states for access to and from on-chip peripheral modules interrupt vector area (48 bytes) on-chip rom on-chip ram 32-byte serial data buffer internal i/o registers (96 bytes) internal i/o registers (64 bytes) reserved 60 kbytes * 1 1,024 bytes h'0000 h'002f h'0030 h'edff * 1 h'f740 h'f77f h'fb80 h'ff7f h'ff80 h'ff9f h'ffa0 h'ffff word byte access states 2 or 3 * 2 2 ? ? ? 2 or 3 * 2 2 ? ? ? 2 o o o o o o o o : access possible : not possible reserved notes: the h8/3927 is shown as an example. 1. 2. the h8/3926 rom occupies 48 kbytes up to address h'bfff. the h8/3925 rom occupies 40 kbytes up to address h'9fff. the h8/3924 rom occupies 32 kbytes up to address h'7fff. internal i/o registers defined in areas assigned to timer x (h'f770 to h'f77f) and timer v (h'ffb8 to h'ffbd) are accessed in three states. 49 2.9.2 notes on bit manipulation the bset, bclr, bnot, bst, and bist instructions read one byte of data, modify the data, then write the data byte again. special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include write-only bits, and when the instruction accesses an i/o port. order of operation operation 1 read read byte data at the designated address 2 modify modify a designated bit in the read data 3 write write the altered byte data to the designated address 1. bit manipulation in two registers assigned to the same address example 1: timer load register and timer counter figure 2-18 shows an example in which two timer registers share the same address. when a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place. order of operation operation 1 read timer counter data is read (one byte) 2 modify the cpu modifies (sets or resets) the bit designated in the instruction 3 write the altered byte data is written to the timer load register the timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. as a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. figure 2-18 timer configuration example h124 h8/3834 '92 fig. 2-18 r w r: w: read write count clock timer counter timer load register reload internal bus 50 example 2: bset instruction executed designating port 3 p3 7 and p3 6 are designated as input pins, with a low-level signal input at p3 7 and a high-level signal at p3 6 . the remaining pins, p3 5 to p3 0 , are output pins and output low-level signals. in this example, the bset instruction is used to change pin p3 0 to high-level output. [a: prior to executing bset] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low high low low low low low low level level level level level level level level pcr3 0 0 1 1 1 1 1 1 pdr3 1 0 0 0 0 0 0 0 [b: bset instruction executed] the bset instruction is executed designating port 3. [c: after executing bset] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low high low low low low low high level level level level level level level level pcr3 0 0 1 1 1 1 1 1 pdr3 0 1 0 0 0 0 0 1 [d: explanation of how bset operates] when the bset instruction is executed, first the cpu reads port 3. since p3 7 and p3 6 are input pins, the cpu reads the pin states (low-level and high-level input). p3 5 to p3 0 are output pins, so the cpu reads the value in pdr3. in this example pdr3 has a value of h'80, but the value read by the cpu is h'40. next, the cpu sets bit 0 of the read data to 1, changing the pdr3 data to h'41. finally, the cpu writes this value (h'41) to pdr3, completing execution of bset. bset #0 , @pdr3 51 as a result of this operation, bit 0 in pdr3 becomes 1, and p3 0 outputs a high-level signal. however, bits 7 and 6 of pdr3 end up with different values. to avoid this problem, store a copy of the pdr3 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pdr3. [a: prior to executing bset] the pdr3 value (h'80) is written to a work area in memory (ram0) as well as to pdr3. p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low high low low low low low low level level level level level level level level pcr3 0 0 1 1 1 1 1 1 pdr3 1 0 0 0 0 0 0 0 ram0 1 0 0 0 0 0 0 0 [b: bset instruction executed] the bset instruction is executed designating the pdr3 work area (ram0). bset #0 , @ram0 mov. b #80, r0l mov. b r0l, @ram0 mov. b r0l, @pdr3 52 [c: after executing bset] the work area (ram0) value is written to pdr3. p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low high low low low low low high level level level level level level level level pcr3 0 0 1 1 1 1 1 1 pdr3 1 0 0 0 0 0 0 1 ram0 1 0 0 0 0 0 0 1 2. bit manipulation in a register containing a write-only bit example 3: bclr instruction executed designating port 3 control register pcr3 as in the examples above, p3 7 and p3 6 are input pins, with a low-level signal input at p3 7 and a high-level signal at p3 6 . the remaining pins, p3 5 to p3 0 , are output pins that output low-level signals. in this example, the bclr instruction is used to change pin p3 0 to an input port. it is assumed that a high-level signal will be input to this input pin. [a: prior to executing bclr] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low high low low low low low low level level level level level level level level pcr3 0 0 1 1 1 1 1 1 pdr3 1 0 0 0 0 0 0 0 [b: bclr instruction executed] the bclr instruction is executed designating pcr3. bclr #0 , @pcr3 mov. b @ram0, r0l mov. b r0l, @pdr3 53 [c: after executing bclr] p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output output output output output output output output input pin state low high low low low low low high level level level level level level level level pcr3 1 1 1 1 1 1 1 0 pdr3 1 0 0 0 0 0 0 0 [d: explanation of how bclr operates] when the bclr instruction is executed, first the cpu reads pcr3. since pcr3 is a write-only register, the cpu reads a value of h'ff, even though the pcr3 value is actually h'3f. next, the cpu clears bit 0 in the read data to 0, changing the data to h'fe. finally, this value (h'fe) is written to pcr3 and bclr instruction execution ends. as a result of this operation, bit 0 in pcr3 becomes 0, making p3 0 an input port. however, bits 7 and 6 in pcr3 change to 1, so that p3 7 and p3 6 change from input pins to output pins. to avoid this problem, store a copy of the pcr3 data in a work area in memory. perform the bit manipulation on the data in the work area, then write this data to pcr3. [a: prior to executing bclr] the pcr3 value (h'3f) is written to a work area in memory (ram0) as well as to pcr3. p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low high low low low low low low level level level level level level level level pcr3 0 0 1 1 1 1 1 1 pdr3 1 0 0 0 0 0 0 0 ram0 0 0 1 1 1 1 1 1 mov. b #3f, r0l mov. b r0l, @ram0 mov. b r0l, @pcr3 54 [b: bclr instruction executed] the bclr instruction is executed designating the pcr3 work area (ram0). [c: after executing bclr] the work area (ram0) value is written to pcr3. p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 input/output input input output output output output output output pin state low high low low low low low high level level level level level level level level pcr3 0 0 1 1 1 1 1 0 pdr3 1 0 0 0 0 0 0 0 ram0 0 0 1 1 1 1 1 0 table 2-12 lists the pairs of registers that share identical addresses. table 2-13 lists the registers that contain write-only bits. table 2-12 registers with shared addresses register name abbreviation address output compare register ah and output compare register bh (timer x) ocrah/ocrbh h'f774 output compare register al and output compare register bl (timer x) ocral/ocrbl h'f775 timer counter b1 and timer load register b1 (timer b1) tcb1/tlb1 h'ffb3 timer counter b2 and timer load register b2 (timer b2) tcb2/tlb2 h'ffc3 timer counter b3 and timer load register b3 (timer b3) tcb3/tlb3 h'ffe3 timer counter c and timer load register c (timer c) tcc/tlc h'ffb5 timer counter e and timer load register e (timer e) tce/tle h'ffb7 timer counter yh and timer load register yh (timer y) tcyh/tlyh h'ffce timer counter yl and timer load register yl (timer y) tcyl/tlyl h'ffcf port data register 1 * pdr1 h'ffd4 port data register 3 * pdr3 h'ffd6 port data register 4 * pdr4 h'ffd7 port data register 5 * pdr5 h'ffd8 port data register 6 * pdr6 h'ffd9 port data register 7 * pdr7 h'ffda port data register 8 * pdr8 h'ffdb note: * port data registers have the same addresses as input pins. mov. b @ram0, r0l mov. b r0l, @pcr3 bclr #0 , @ram0 55 table 2-13 registers with write-only bits register name abbreviation address port control register 1 pcr1 h'ffe4 port control register 3 pcr3 h'ffe6 port control register 4 pcr4 h'ffe7 port control register 5 pcr5 h'ffe8 port control register 6 pcr6 h'ffe9 port control register 7 pcr7 h'ffea port control register 8 pcr8 h'ffeb pwm control register pwcr h'ffd0 pwm data register u pwdru h'ffd1 pwm data register l pwdrl h'ffd2 2.9.3 notes on use of the eepmov instruction the eepmov instruction is a block data transfer instruction. it moves the number of bytes specified by r4l from the address specified by r5 to the address specified by r6. when setting r4l and r6, make sure that the final destination address (r6 + r4l) does not exceed h'ffff. the value in r6 must not change from h'ffff to h'0000 during execution of the instruction. h'ffff not allowed h8/3834 '92 2.9.3 (2) ? r6 ? r6 + r4l r5 ? r5 + r4l ? ? r6 ? r6 + r4l r5 ? r5 + r4l ? h8/3834 '92 2.9.3 (1) 56 section 3 exception handling 3.1 overview exception handling is performed in the h8/3927 series when a reset or interrupt occurs. table 3-1 shows the priorities of these two types of exception handling. table 3-1 exception handling types and priorities priority exception source time of start of exception handling high reset exception handling starts as soon as the reset state is cleared interrupt when an interrupt is requested, exception handling starts after execution of the present instruction or the exception low handling in progress is completed 3.2 reset 3.2.1 overview a reset is the highest-priority exception. the internal state of the cpu and the registers of the on- chip peripheral modules are initialized. 3.2.2 reset sequence 1. reset by res pin as soon as the res pin goes low, all processing is stopped and the chip enters the reset state. to make sure the chip is reset properly, observe the following precautions. at power on: hold the res pin low until the clock pulse generator output stabilizes. resetting during operation: hold the res pin low for at least 10 system clock cycles. reset exception handling begins when the res pin is held low for a given period, then returned to the high level. reset exception handling takes place as follows. the cpu internal state and the registers of on-chip peripheral modules are initialized, with the i bit of the condition code register (ccr) set to 1. the pc is loaded from the reset exception handling vector address (h'0000 to h'0001), after which the program starts executing from the address indicated in pc. 57 when system power is turned on or off, the res pin should be held low. figure 3-1 shows the reset sequence starting from res input. figure 3-1 reset sequence 2. reset by watchdog timer the watchdog timer counter (tcw) starts counting up when the wdon bit is set to 1 in the watchdog timer control/status register (tcsrw). if tcw overflows, the wrst bit is set to 1 in tcsrw and the chip enters the reset state. while the wrst bit is set to 1 in tcsrw, when tcw overflows the reset state is cleared and reset exception handling begins. the same reset exception handling is carried out as for input at the res pin. for details on the watchdog timer, see 9.11, watchdog timer. vector fetch internal address bus internal read signal internal write signal internal data bus (16-bit) res internal processing program initial instruction prefetch (1) reset exception handling vector address (h'0000) (2) program start address (3) first instruction of program (2) (3) (2) (1) reset cleared 58 3.2.3 interrupt immediately after reset after a reset, if an interrupt were to be accepted before the stack pointer (sp: r7) was initialized, pc and ccr would not be pushed onto the stack correctly, resulting in program runaway. to prevent this, immediately after reset exception handling all interrupts are masked. for this reason, the initial program instruction is always executed immediately after a reset. this instruction should initialize the stack pointer (e.g. mov.w #xx: 16, sp). 3.3 interrupts 3.3.1 overview the interrupt sources include 13 external interrupts (nmi, irq 3 to irq 0 , int 7 to int 0 ) and 22 internal interrupts from on-chip peripheral modules. table 3-2 shows the interrupt sources, their priorities, and their vector addresses. when more than one interrupt is requested, the interrupt with the highest priority is processed. the interrupts have the following features: nmi has the highest priority and is always accepted. the other internal and external interrupts can be masked by the i bit in ccr. when the i bit is set to 1, interrupt request flags can be set but the interrupts are not accepted, except for nmi. nmi, irq 3 to irq 0 , and int 7 to int 0 can be set independently to either rising edge sensing or falling edge sensing. 59 table 3-2 interrupt sources and their priorities interrupt source interrupt vector number vector address priority res reset 0 h'0000 to h'0001 high nmi nmi 3 h'0006 to h'0007 irq 0 irq 0 4 h'0008 to h'0009 irq 1 irq 1 5 h'000a to h'000b irq 2 irq 2 6 h'000c to h'000d irq 3 irq 3 7 h'000e to h'000f int 0 int 0 8 h'0010 to h'0011 int 1 int 1 int 2 int 2 int 3 int 3 int 4 int 4 int 5 int 5 int 6 int 6 int 7 int 7 timer y timer y overflow 9 h'0012 to h'0013 timer a timer a overflow 10 h'0014 to h'0015 timer b1 timer b1 overflow 11 h'0016 to h'0017 timer b2 timer b2 overflow 12 h'0018 to h'0019 timer b3 timer b3 overflow 13 h'001a to h'001b timer c timer c overflow or underflow 14 h'001c to h'001d timer e timer e overflow 15 h'001e to h'001f timer x timer x input capture a 16 h'0020 to h'0021 timer x input capture b timer x input capture c timer x input capture d timer x compare match a timer x compare match b timer x overflow timer v timer v compare match a 17 h'0022 to h'0023 timer v compare match b timer v overflow sci1 sci1 transfer complete 19 h'0026 to h'0027 sci2 sci2 transfer complete 20 h'0028 to h'0029 sci2 transfer abort a/d a/d conversion end 22 h'002c to h'002d (sleep instruction direct transfer 23 h'002e to h'002f low executed) note: * vector addresses h'0002 to h'0005, h'0024 to h'0025, and h'002a to h'002b are reserved and cannot be used. 60 3.3.2 interrupt control registers table 3-3 lists the registers that control interrupts. table 3-3 interrupt control registers name abbreviation r/w initial value address interrupt edge select register 1 iegr1 r/w h'70 h'fff2 interrupt edge select register 2 iegr2 r/w h'00 h'fff3 interrupt enable register 1 ienr1 r/w h'10 h'fff4 interrupt enable register 2 ienr2 r/w h'00 h'fff5 interrupt enable register 3 ienr3 r/w h'00 h'fff6 interrupt request register 1 irr1 r/w * h'10 h'fff7 interrupt request register 2 irr2 r/w * h'00 h'fff8 interrupt request register 3 irr3 r/w * h'00 h'fff9 note: * write is enabled only for writing of 0 to clear a flag. 1. interrupt edge select register 1 (iegr1) iegr1 is an 8-bit read/write register, used to designate whether pins nmi and irq 3 to irq 0 are set to rising edge sensing or falling edge sensing. upon reset, iegr1 is initialized to h'70. bit 7: nmi edge select (nmieg) bit 7 selects the input sensing of the nmi pin. bit 7 nmieg description 0 falling edge of nmi pin input is detected (initial value) 1 rising edge of nmi pin input is detected bits 6 to 4: reserved bits bits 6 to 4 are reserved; they are always read as 1, and cannot be modified. bit initial value read/write 7 nmieg 0 r/w 6 ? 1 5 ? 1 4 ? 1 3 ieg3 0 r/w 0 ieg0 0 r/w 2 ieg2 0 r/w 1 ieg1 0 r/w 61 bit 3: irq 3 edge select (ieg3) bit 3 selects the input sensing of pin irq 3 . bit 3 ieg3 description 0 falling edge of irq 3 pin input is detected (initial value) 1 rising edge of irq 3 pin input is detected bit 2: irq 2 edge select (ieg2) bit 2 selects the input sensing of pin irq 2 . bit 2 ieg2 description 0 falling edge of irq 2 pin input is detected (initial value) 1 rising edge of irq 2 pin input is detected bit 1: irq 1 edge select (ieg1) bit 1 selects the input sensing of pin irq 1 . bit 1 ieg1 description 0 falling edge of irq 1 pin input is detected (initial value) 1 rising edge of irq 1 pin input is detected bit 0: irq 0 edge select (ieg0) bit 0 selects the input sensing of pin irq 0 . bit 0 ieg0 description 0 falling edge of irq 0 pin input is detected (initial value) 1 rising edge of irq 0 pin input is detected 62 2. interrupt edge select register 2 (iegr2) iegr2 is an 8-bit read/write register, used to designate whether pins int 7 to int 0 , tmiy, and tmib are set to rising edge sensing or falling edge sensing. upon reset, iegr2 is initialized to h'00. bit 7: int 7 edge select (integ7) bit 7 selects the input sensing of the int 7 pin and tmiy pin. bit 7 integ7 description 0 falling edge of int 7 and tmiy pin input is detected (initial value) 1 rising edge of int 7 and tmiy pin input is detected bit 6: int 6 edge select (integ6) bit 6 selects the input sensing of the int 6 pin and tmib pin. bit 6 integ6 description 0 falling edge of int 6 and tmib pin input is detected (initial value) 1 rising edge of int 6 and tmib pin input is detected bits 5 to 0: int 5 to int 0 edge select (integ5 to integ0) bits 5 to 0 select the input sensing of pins int 5 to int 0 . bit n integn description 0 falling edge of int n pin input is detected (initial value) 1 rising edge of int n pin input is detected (n = 5 to 0) bit initial value read/write 7 integ7 0 r/w 6 integ6 0 r/w 5 integ5 0 r/w 4 integ4 0 r/w 3 integ3 0 r/w 0 integ0 0 r/w 2 integ2 0 r/w 1 integ1 0 r/w 63 3. interrupt enable register 1 (ienr1) ienr1 is an 8-bit read/write register that enables or disables interrupt requests. upon reset, ienr1 is initialized to h'10. bit 7: timer b1 interrupt enable (ientb1) bit 7 enables or disables timer b1 overflow interrupt requests. bit 7 ientb1 description 0 disables timer b1 interrupt requests (initial value) 1 enables timer b1 interrupt requests bit 6: timer a interrupt enable (ienta) bit 6 enables or disables timer a overflow interrupt requests. bit 6 ienta description 0 disables timer a interrupt requests (initial value) 1 enables timer a interrupt requests bit 5: timer y interrupt enable (ienty) bit 5 enables or disables timer y overflow interrupt requests. bit 5 ienty description 0 disables timer y interrupt requests (initial value) 1 enables timer y interrupt requests bit 4: reserved bit bit 4 is reserved; it is always read as 1, and cannot be modified. bit initial value read/write 7 ientb1 0 r/w 6 ienta 0 r/w 5 ienty 0 r/w 4 ? 1 3 ien3 0 r/w 0 ien0 0 r/w 2 ien2 0 r/w 1 ien1 0 r/w 64 bits 3 to 0: irq 3 to irq 0 interrupt enable (ien3 to ien0) bits 3 to 0 enable or disable irq 3 to irq 0 interrupt requests. bit n ienn description 0 disables interrupt requests from pin irq n (initial value) 1 enables interrupt requests from pin irq n (n = 3 to 0) 4. interrupt enable register 2 (ienr2) ienr2 is an 8-bit read/write register that enables or disables interrupt requests. upon reset, ienr2 is initialized to h'00. bit 7: direct transfer interrupt enable (iendt) bit 7 enables or disables direct transfer interrupt requests. bit 7 iendt description 0 disables direct transfer interrupt requests (initial value) 1 enables direct transfer interrupt requests bit 6: a/d converter interrupt enable (ienad) bit 6 enables or disables a/d converter interrupt requests. bit 6 ienad description 0 disables a/d converter interrupt requests (initial value) 1 enables a/d converter interrupt requests bit initial value read/write 7 iendt 0 r/w 6 ienad 0 r/w 5 iens2 0 r/w 4 iens1 0 r/w 3 iente 0 r/w 0 ientb2 0 r/w 2 ientc 0 r/w 1 ientb3 0 r/w 65 bit 5: sci2 interrupt enable (iens2) bit 5 enables or disables sci2 transfer complete and transfer abort interrupt requests. bit 5 iens2 description 0 disables sci2 interrupt requests (initial value) 1 enables sci2 interrupt requests bit 4: sci1 interrupt enable (iens1) bit 4 enables or disables sci1 transfer complete interrupt requests. bit 4 iens1 description 0 disables sci1 interrupt requests (initial value) 1 enables sci1 interrupt requests bit 3: timer e interrupt enable (iente) bit 3 enables or disables timer e overflow interrupt requests. bit 3 iente description 0 disables timer e interrupt requests (initial value) 1 enables timer e interrupt requests bit 2: timer c interrupt enable (ientc) bit 2 enables or disables timer c overflow and underflow interrupt requests. bit 2 ientc description 0 disables timer c interrupt requests (initial value) 1 enables timer c interrupt requests bit 1: timer b3 interrupt enable (ientb3) bit 1 enables or disables timer b3 overflow interrupt requests. bit 1 ientb3 description 0 disables timer b3 interrupt requests (initial value) 1 enables timer b3 interrupt requests 66 bit 0: timer b2 interrupt enable (ientb2) bit 0 enables or disables timer b2 overflow interrupt requests. bit 0 ientb2 description 0 disables timer b2 interrupt requests (initial value) 1 enables timer b2 interrupt requests 5. interrupt enable register 3 (ienr3) ienr3 is an 8-bit read/write register that enables or disables int 7 to int 0 interrupt requests. upon reset, ienr3 is initialized to h'00. bits 7 to 0: int 7 to int 0 interrupt enable (inten7 to inten0) bits 7 to 0 enable or disable int 7 to int 0 interrupt requests. bit n intenn description 0 disables interrupt requests from pin int n (initial value) 1 enables interrupt requests from pin int n (n = 7 to 0) 6. interrupt request register 1 (irr1) irr1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer b1, timer a, timer y, or irq 3 to irq 0 interrupt is requested. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. upon reset, irr1 is initialized to h'10. bit initial value read/write 7 irrtb1 0 r/w 6 irrta 0 r/w 5 irrty 0 r/w 4 ? 1 3 irri3 0 r/w 0 irri0 0 r/w 2 irri2 0 r/w 1 irri1 0 r/w * * * * * * * note: * only a write of 0 for flag clearing is possible bit initial value read/write 7 inten7 0 r/w 6 inten6 0 r/w 5 inten5 0 r/w 4 inten4 0 r/w 3 inten3 0 r/w 0 inten0 0 r/w 2 inten2 0 r/w 1 inten1 0 r/w 67 bit 7: timer b1 interrupt request flag (irrtb1) bit 7 irrtb1 description 0 clearing conditions: (initial value) when irrtb1 = 1, it is cleared by writing 0 1 setting conditions: when the timer b1 counter value overflows from h'ff to h'00 bit 6: timer a interrupt request flag (irrta) bit 6 irrta description 0 clearing conditions: (initial value) when irrta = 1, it is cleared by writing 0 1 setting conditions: when the timer a counter value overflows from h'ff to h'00 bit 5: timer y interrupt request flag (irrty) bit 5 irrty description 0 clearing conditions: (initial value) when irrty = 1, it is cleared by writing 0 1 setting conditions: when the timer y counter value overflows from h'ffff to h'0000 bit 4: reserved bit bit 4 is reserved; it is always read as 1, and cannot be modified. bits 3 to 0: irq 3 to irq 0 interrupt request flags (irri3 to irri0) bit n irrin description 0 clearing conditions: (initial value) when irrin = 1, it is cleared by writing 0 1 setting conditions: when pin irq n is designated for interrupt input and the designated signal edge is input (n = 3 to 0) 68 7. interrupt request register 2 (irr2) irr2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct transfer, a/d converter, sci2, sci1, timer e, timer c, timer b3, or timer b2 interrupt is requested. the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. upon reset, irr2 is initialized to h'00. bit 7: direct transfer interrupt request flag (irrdt) bit 7 irrdt description 0 clearing conditions: (initial value) when irrdt = 1, it is cleared by writing 0 1 setting conditions: when a direct transfer is made by executing a sleep instruction while dton = 1 in syscr2 bit 6: a/d converter interrupt request flag (irrad) bit 6 irrad description 0 clearing conditions: (initial value) when irrad = 1, it is cleared by writing 0 1 setting conditions: when a/d conversion is completed and adsf is cleared to 0 in adsr bit 5: sci2 interrupt request flag (irrs2) bit 5 irrs2 description 0 clearing conditions: (initial value) when irrs2 = 1, it is cleared by writing 0 1 setting conditions: when an sci2 transfer is completed or aborted bit initial value read/write 7 irrdt 0 r/w 6 irrad 0 r/w 5 irrs2 0 r/w 4 irrs1 0 r/w 3 irrte 0 r/w 0 irrtb2 0 r/w 2 irrtc 0 r/w 1 irrtb3 0 r/w * * * * * * * * note: * only a write of 0 for flag clearing is possible 69 bit 4: sci1 interrupt request flag (irrs1) bit 4 irrs1 description 0 clearing conditions: (initial value) when irrs1 = 1, it is cleared by writing 0 1 setting conditions: when an sci1 transfer is completed bit 3: timer e interrupt request flag (irrte) bit 3 irrte description 0 clearing conditions: (initial value) when irrte = 1, it is cleared by writing 0 1 setting conditions: when the timer e counter value overflows from h'ff to h'00 bit 2: timer c interrupt request flag (irrtc) bit 2 irrtc description 0 clearing conditions: (initial value) when irrtc = 1, it is cleared by writing 0 1 setting conditions: when the timer c counter value overflows from h'ff to h'00 or underflows from h'00 to h'ff bit 1: timer b3 interrupt request flag (irrtb3) bit 1 irrtb3 description 0 clearing conditions: (initial value) when irrtb3 = 1, it is cleared by writing 0 1 setting conditions: when the timer b3 counter value overflows from h'ff to h'00 bit 0: timer b2 interrupt request flag (irrtb2) bit 0 irrtb2 description 0 clearing conditions: (initial value) when irrtb2 = 1, it is cleared by writing 0 1 setting conditions: when the timer b2 counter value overflows from h'ff to h'00 70 8. interrupt request register 3 (irr3) irr3 is an 8-bit read/write register, in which a corresponding flag is set to 1 by a transition at pin int 7 to int 0 . the flags are not cleared automatically when an interrupt is accepted. it is necessary to write 0 to clear each flag. upon reset, irr3 is initialized to h'00. bits 7 to 0: int 7 to int 0 interrupt request flags (intf7 to intf0) bit n intfn description 0 clearing conditions: (initial value) when intfn = 1, it is cleared by writing 0 1 setting conditions: when the designated signal edge is input at pin int n (n = 7 to 0) note: pins int 7 to int 0 are multiplexed with port 5. even in port usage of these pins, whenever the designated edge is input or output, the corresponding bit intfn is set to 1. 3.3.3 external interrupts there are 13 external interrupts: nmi, irq 3 to irq 0 , an int 7 to int 0 . 1. nmi interrupt the nmi interrupt is requested by input at the nmi pin. this interrupt can be detected by either rising edge sensing or falling edge sensing, depending on the setting of bit nmieg in iegr1. the nmi interrupt has highest priority and is always accepted, regardless of the setting of the i bit in ccr. the nmi interrupt has exception vector 3. when nmi exception handling is initiated, the i bit is set to 1 in ccr. 2. interrupts irq 3 to irq 0 interrupts irq 3 to irq 0 are requested by input signals to pins irq 3 to irq 0 . these interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits ieg3 to ieg0 in iegr1. bit initial value read/write 7 intf7 0 r/w 6 intf6 0 r/w 5 intf5 0 r/w 4 intf4 0 r/w 3 intf3 0 r/w 0 intf0 0 r/w 2 intf2 0 r/w 1 intf1 0 r/w * * * * * * * * note: * only a write of 0 for flag clearing is possible 71 when these pins are designated as pins irq 3 to irq 0 in port mode register 1 and the designated edge is input, the corresponding bit in irr1 is set to 1, requesting an interrupt. recognition of these interrupt requests can be disabled individually by clearing bits ien3 to ien0 to 0 in ienr1. these interrupts can all be masked by setting the i bit to 1 in ccr. when irq 3 to irq 0 interrupt exception handling is initiated, the i bit is set to 1 in ccr. vector numbers 7 to 4 are assigned to interrupts irq 3 to irq 0 . the order of priority is from irq 0 (high) to irq 3 (low). table 3-2 gives details. 3. int interrupts int interrupts are requested by input signals to pins int 7 to int 0 . these interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits integ7 to integ0 in iegr2. when the designated edge is input at pins int 7 to int 0 , the corresponding bit in irr1 is set to 1, requesting an interrupt. recognition of these interrupt requests can be disabled individually by clearing bits inten7 to inten0 to 0 in ienr3. these interrupts can all be masked by setting the i bit to 1 in ccr. when int interrupt exception handling is initiated, the i bit is set to 1 in ccr. vector number 8 is assigned to the int interrupts. all eight interrupts have the same vector number, so the interrupt- handling routine must discriminate the interrupt source. note: pins int 7 to int 0 are multiplexed with port 5. even in port usage of these pins, whenever the designated edge is input or output, the corresponding bit intfn is set to 1. 3.3.4 internal interrupts there are 22 internal interrupts that can be requested by the on-chip peripheral modules. when a peripheral module requests an interrupt, the corresponding bit in irr1 or irr2 is set to 1. recognition of individual interrupt requests can be disabled by clearing the corresponding bit in ienr1 or ienr2. all these interrupts can be masked by setting the i bit to 1 in ccr. when internal interrupt handling is initiated, the i bit is set to 1 in ccr. vector numbers from 23 to 9 are assigned to these interrupts. table 3-2 shows the order of priority of interrupts from on-chip peripheral modules. 72 3.3.5 interrupt operations interrupts are controlled by an interrupt controller. figure 3-2 shows a block diagram of the interrupt controller. figure 3-3 shows the flow up to interrupt acceptance. figure 3-2 block diagram of interrupt controller interrupt operation is described as follows. when an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. when the interrupt controller receives an interrupt request, it sets the interrupt request flag. from among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (refer to table 3-2 for a list of interrupt priorities.) the interrupt controller checks the i bit of ccr. if the i bit is 0, the selected interrupt request is accepted; if the i bit is 1, the interrupt request is held pending. interrupt controller priority decision logic interrupt request ccr (cpu) i external or internal interrupts external interrupts or internal interrupt enable signals nmi request nmi interrupt 73 if the interrupt is accepted, after processing of the current instruction is completed, both pc and ccr are pushed onto the stack. the state of the stack at this time is shown in figure 3-4. the pc value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. the i bit of ccr is set to 1, masking further interrupts. the vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed. notes: 1. when disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt request register, always do so while interrupts are masked (i = 1). 2. if the above clear operations are performed while i = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed. 74 figure 3-3 flow up to interrupt acceptance h037 '92 h8/3834 u.m. fig. 3-4 pc contents saved ccr contents saved i ? 1 i = 0 program execution state no yes yes no notation: pc: ccr: i: program counter condition code register i bit of ccr ieno = 1 no yes iendt = 1 no yes irrdt = 1 no yes branch to interrupt handling routine irrio = 1 no yes ien1 = 1 no yes irri1 = 1 no yes ien2 = 1 no yes irri2 = 1 nmi? no yes 75 figure 3-4 stack state after completion of interrupt exception handling figure 3-5 shows a typical interrupt sequence where the program area is in the on-chip rom and the stack area is in the on-chip ram. pc and ccr saved to stack sp (r7) sp ?1 sp ?2 sp ?3 sp ?4 stack area sp + 4 sp + 3 sp + 2 sp + 1 sp (r7) even address prior to start of interrupt exception handling after completion of interrupt exception handling notation: pc h : pc l : ccr: sp: upper 8 bits of program counter (pc) lower 8 bits of program counter (pc) condition code register stack pointer * ignored on return from interrupt. notes: ccr ccr * pc h pc l h037 '92 h8/3834 u.m. fig. 3-5 1. 2. pc shows the address of the first instruction to be executed upon return from the interrupt handling routine. register contents must always be saved and restored by word access, starting from an even-numbered address. 76 figure 3-5 interrupt sequence vector fetch internal address bus internal read signal internal write signal (2) internal data bus (16 bits) interrupt request signal (9) (1) internal processing prefetch instruction of interrupt-handling routine (1) instruction prefetch address (instruction is not executed. address is saved as pc contents, becoming return address.) (2)(4) instruction code (not executed) (3) instruction prefetch address (instruction is not executed.) (5) sp ?2 (6) sp ?4 (7) ccr (8) vector address (9) starting address of interrupt-handling routine (contents of vector) (10) first instruction of interrupt-handling routine (3) (9) (8) (6) (5) (4) (1) (7) (10) stack access internal processing instruction prefetch interrupt level decision and wait for end of instruction interrupt is accepted h037 '92 h8/3834 u.m. fig. 3-6 77 3.3.6 interrupt response time table 3-4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. table 3-4 interrupt wait states item states waiting time for completion of executing instruction * 1 to 13 saving of pc and ccr to stack 4 vector fetch 2 instruction fetch 4 internal processing 4 total 15 to 27 note: * not including eepmov instruction. 78 3.4 application notes 3.4.1 notes on stack area use when word data is accessed in the h8/3927 series, the least significant bit of the address is regarded as 0. access to the stack always takes place in word size, so the stack pointer (sp: r7) should never indicate an odd address. use push rn (mov.w rn, @?p) or pop rn (mov.w @sp+, rn) to save or restore register values. setting an odd address in sp may cause a program to crash. an example is shown in figure 3-6. figure 3-6 operation when odd address is set in sp when ccr contents are saved to the stack during interrupt exception handling or restored when rte is executed, this also takes place in word size. both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to ccr while the odd address contents are ignored. h037 '92 h8/3834 u.m. fig. 3-7 pc pc r1l pc sp sp sp h'fefc h'fefd h'feff ? ? ? h l l mov. b r1l, @?7 sp set to h'feff stack accessed beyond sp bsr instruction contents of pc are lost h notation: pc h : pc l : r1l: sp: upper byte of program counter lower byte of program counter general register r1l stack pointer 79 3.4.2 notes on rewriting port mode registers when a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. when an external interrupt pin function is switched by rewriting the port mode register that controls pins irq 3 to irq 1 , the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. be sure to clear the interrupt request flag to 0 after switching pin functions. table 3-5 shows the conditions under which interrupt request flags are set to 1 in this way. table 3-5 conditions under which interrupt request flag is set to 1 interrupt request flags set to 1 conditions irr1 irri3 when pmr1 bit irq3 is changed from 0 to 1 while pin irq 3 is low and iegr bit ieg3 = 0. when pmr1 bit irq3 is changed from 1 to 0 while pin irq 3 is low and iegr bit ieg3 = 1. irri2 when pmr1 bit irq2 is changed from 0 to 1 while pin irq 2 is low and iegr bit ieg2 = 0. when pmr1 bit irq2 is changed from 1 to 0 while pin irq 2 is low and iegr bit ieg2 = 1. irri1 when pmr1 bit irq1 is changed from 0 to 1 while pin irq 1 is low and iegr bit ieg1 = 0. when pmr1 bit irq1 is changed from 1 to 0 while pin irq 1 is low and iegr bit ieg1 = 1. figure 3-7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. when switching a pin function, mask the interrupt before setting the bit in the port mode register. after accessing the port mode register, execute at least one instruction (e.g., nop), then clear the interrupt request flag from 1 to 0. if the instruction to clear the flag is executed immediately after the port mode register access without executing an intervening instruction, the flag will not be cleared. an alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3-5 do not occur. 80 figure 3-7 port mode register setting and interrupt request flag clearing procedure h124 '92 fig. 3-8 ccr i bit 1 set port mode register bit execute nop instruction interrupts masked. (another possibility is to disable the relevant interrupt in interrupt enable register 1.) after setting the port mode register bit, first execute at least one instruction (e.g., nop), then clear the interrupt request flag to 0 interrupt mask cleared clear interrupt request flag to 0 ? ccr i bit 0 ? 81 section 4 clock pulse generators 4.1 overview clock oscillator circuitry (cpg: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. the system clock pulse generator consists of a system clock oscillator and system clock dividers. the subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. 4.1.1 block diagram figure 4-1 shows a block diagram of the clock pulse generators. figure 4-1 block diagram of clock pulse generators 4.1.2 system clock and subclock the basic clock signals that drive the cpu and on-chip peripheral modules are ?and sub . four of the clock signals have names: ?is the system clock, sub is the subclock, osc is the oscillator clock, and w is the watch clock. the clock signals available for use by peripheral modules are ?2, ?4, ?8, ?16, ?32, ?64, ?128, ?256, ?512, ?1024, ?2048, ?4096, ?8192, w /2, w /4, w /8, w /16, w /32, w /64, and w /128. the clock requirements differ from one module to another. system clock oscillator system clock divider (1/2) subclock oscillator subclock divider (1/2, 1/4, 1/8) system clock divider (1/64) system clock pulse generator subclock pulse generator prescaler s (13 bits) prescaler w (5 bits) osc osc 1 2 x x 1 2 osc (f ) osc w (f ) w ? /2 osc ? /2 w ? /8 w sub ?2 to ?8192 ? /2 w ? /4 w ? /8 to ? /128 w w osc /128 ? /4 w 83 4.2 system clock generator clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. 1. connecting a crystal oscillator figure 4-2 shows a typical method of connecting a crystal oscillator. figure 4-2 typical connection to crystal oscillator figure 4-3 shows the equivalent circuit of a crystal oscillator. an oscillator having the characteristics given in table 4-1 should be used. figure 4-3 equivalent circuit of crystal oscillator table 4-1 crystal oscillator parameters frequency 2 4 8 10 r s max ( ) 500 100 50 30 c 0 (pf) 7 pf max c s c 0 r s osc 1 osc 2 h8/3834 '92 fig. 4-3 l s 1 2 c 1 c 2 h8/3834 '92 fig. 4-2 osc osc r = 1 m ?0% c = c = 12 pf ?0% f 1 2 w r f 84 2. connecting a ceramic oscillator figure 4-4 shows a typical method of connecting a ceramic oscillator. figure 4-4 typical connection to ceramic oscillator 3. notes on board design when generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (see figure 4-5.) the board should be designed so that the oscillator and load capacitors are located as close as possible to pins osc 1 and osc 2 . figure 4-5 board design of oscillator circuit osc osc c 2 c 1 signal a signal b 2 1 to be avoided h8/3834 '92 fig. 4-5 1 2 c 1 c 2 h8/3834 '92 fig. 4-4 osc osc r = 1 m ?0% c = 30 pf ?0% c = 30 pf ?0% ceramic oscillator: murata f 1 2 w r f 85 4. external clock input method connect an external clock signal to pin osc 1 , and leave pin osc 2 open. figure 4-6 shows a typical connection. figure 4-6 external clock input (example) frequency oscillator clock ( osc ) duty cycle 45% to 55% 1 2 h8/3834 '92 fig. 4-6 osc osc external clock input open 86 4.3 subclock generator 1. connecting a 32.768-khz crystal oscillator clock pulses can be supplied to the subclock divider by connecting a 32.768-khz crystal oscillator, as shown in figure 4-7. follow the same precautions as noted under 4.2.3 for the system clock. figure 4-7 typical connection to 32.768-khz crystal oscillator (subclock) figure 4-8 shows the equivalent circuit of the 32.768-khz crystal oscillator. figure 4-8 equivalent circuit of 32.768-khz crystal oscillator c s c 0 l r s x 1 x 2 h8/3834 '92 fig. 4-8 c = 1.5 pf typ r = 14 k typ f = 32.768 khz crystal oscillator: 0 s w w s mx38t (nihon denpa kogyo) x x c 1 c 2 1 2 h8/3834 '92 fig. 4-7 c = c = 15 pf (typ.) 1 2 87 2. pin connection when not using subclock when the subclock is not used, connect pin x 1 to v cc and leave pin x 2 open, as shown in figure 4-9. figure 4-9 pin connection when not using subclock x x 1 2 v cc open h8/3834 '92 fig. 4-9 88 4.4 prescalers the h8/3927 series is equipped with two on-chip prescalers having different input clocks (prescaler s and prescaler w). prescaler s is a 13-bit counter using the system clock (? as its input clock. its prescaled outputs provide internal clock signals for on-chip peripheral modules. prescaler w is a 5- bit counter using a 32.768-khz signal divided by 4 ( w /4) as its input clock. its prescaled outputs are used by timer a as a time base for timekeeping. 1. prescaler s (pss) prescaler s is a 13-bit counter using the system clock (? as its input clock. it is incremented once per clock period. prescaler s is initialized to h'0000 by a reset, and starts counting on exit from the reset state. in standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. prescaler s also stops and is initialized to h'0000. the cpu cannot read or write prescaler s. the output from prescaler s is shared by the on-chip peripheral modules. the divider ratio can be set separately for each on-chip peripheral function. in active (medium-speed) mode the clock input to prescaler s is osc /128. 2. prescaler w (psw) prescaler w is a 5-bit counter using a 32.768 khz signal divided by 4 ( w /4) as its input clock. prescaler w is initialized to h'00 by a reset, and starts counting on exit from the reset state. even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler w continues functioning so long as clock signals are supplied to pins x 1 and x 2 . prescaler w can be reset by setting 1s in bits tma3 and tma2 of timer mode register a (tma). output from prescaler w can be used to drive timer a, in which case timer a functions as a time base for timekeeping. 89 4.5 note on oscillators oscillator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. suitable constants should be determined in consultation with the oscillator element manufacturer. design the circuit so that the oscillator element never receives voltages exceeding its maximum rating. 90 section 5 power-down modes 5.1 overview the h8/3927 series has eight modes of operation after a reset. these include seven power-down modes, in which power dissipation is significantly reduced. table 5-1 gives a summary of the eight operating modes. table 5-1 operating modes operating mode description active (high-speed) mode the cpu and all on-chip peripheral functions are operable on the system clock active (medium-speed) mode the cpu and all on-chip peripheral functions are operable on the system clock, but at 1/64 the speed in active (high-speed) mode subactive mode the cpu, timer c, and the time-base function of timer a are operable on the subclock sleep (high-speed) mode the cpu halts. on-chip peripheral functions except pwm are operable on the system clock sleep (medium-speed) mode the cpu halts. on-chip peripheral functions except pwm are operable on the system clock, but at 1/64 the speed in active (high-speed) mode subsleep mode the cpu halts. timer c and the time-base function of timer a are operable on the subclock watch mode the cpu halts. the time-base function of timer a is operable on the subclock standby mode the cpu and all on-chip peripheral functions halt of these eight operating modes, all but the active (high-speed) mode are power-down modes. in this section the two active modes (high-speed and medium speed) will be referred to collectively as active mode, and the two sleep modes (high-speed and medium speed) will be referred to collectively as sleep mode. 91 figure 5-1 shows the transitions among these operation modes. table 5-2 indicates the internal states in each mode. figure 5-1 mode transition diagram reset state program halt state sleep instruction * g sleep instruction * h sleep instruction * c sleep instruction * e sleep instruction * f sleep instruction * e sleep instruction * d program execution state sleep instruction * a program halt state sleep instruction * f power-down modes a transition between different modes cannot be made to occur simply because an interrupt request is generated. make sure that interrupt handling is performed after the interrupt is accepted. details on the mode transition conditions are given in the explanations of each mode, in sections 5-2 through 5-8. notes: 1. 2. mode transition conditions (1) * a * b * c * d * e * f * g * h lson mson ssby dton 0 0 1 0 0 1 0 [ 0 1 [ 0 1 [ [ [ 0 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 [ don? care mode transition conditions (2) * 1 interrupt sources timer a interrupt, irq 0 interrupt timer a interrupt, timer c interrupt, irq 3 to irq 0 interrupts, int interrupts, nmi interrupt all interrupts irq 1 , irq 0 , or nmi interrupt timer a interrupt, irq 0 interrupt, nmi interrupt * 2 * 3 * 4 * 5 * 3 * 6 * 2 * 1 * 4 * 4 * 5 standby mode watch mode subactive mode active (medium-speed) mode active (high-speed) mode sleep (high-speed) mode sleep (medium-speed) mode subsleep mode sleep instruction * a sleep instruction * h sleep instruction * g sleep instruction * b sleep instruction * d * 5 sleep instruction * h sleep instruction * b tma3 [ [ 1 0 0 1 0 1 all interrupts except a/d converter interrupt * 6 92 table 5-2 internal state in each operating mode active mode sleep mode high- medium- high- medium- watch subactive subsleep standby function speed speed speed speed mode mode mode mode system clock oscillator functions functions functions functions halted halted halted halted subclock oscillator functions functions functions functions functions functions functions functions cpu instructions functions functions halted halted halted functions halted halted operations registers retained retained retained retained retained ram i/o ports retained * 1 external nmi functions functions functions functions functions functions functions functions interrupts irq 0 functions functions functions functions functions functions functions functions irq 1 retained * 4 irq 2 retained * 4 irq 3 int 0 functions functions functions functions retained * 4 functions functions retained * 4 int 1 int 2 int 3 int 4 int 5 int 6 int 7 peripheral timer a functions functions functions functions functions * 3 functions * 3 functions * 3 retained functions timer b1 retained retained retained timer b2 timer b3 timer c functions/ functions/ retained * 2 retained * 2 timer e retained retained timer v reset reset reset reset timer x timer y retained retained retained retained watchdog timer sci1 sci2 pwm retained retained a/d converter retained functions d/a converter functions functions functions functions reset * 5 notes: 1. register contents are retained, but output is in high-impedance state. 2. functions only if external clock or internal w /4 clock is selected; otherwise halted and retained. 3. functions if timekeeping time-base function is selected. 4. external interrupt requests are ignored. interrupt request register contents are not altered. 5. data register contents are retained, but output is in high-impedance state. 93 5.1.1 system control registers the operation mode is selected using the system control registers described in table 5-3. table 5-3 system control register name abbreviation r/w initial value address system control register 1 syscr1 r/w h'07 h'fff0 system control register 2 syscr2 r/w h'e0 h'fff1 1. system control register 1 (syscr1) syscr1 is an 8-bit read/write register for control of the power-down modes. upon reset, syscr1 is initialized to h'07. bit 7: software standby (ssby) this bit designates transition to standby mode or watch mode. bit 7 ssby description 0 when a sleep instruction is executed in active mode, a transition (initial value) is made to sleep mode when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode 1 when a sleep instruction is executed in active mode, a transition is made to standby mode or watch mode when a sleep instruction is executed in subactive mode, a transition is made to watch mode h037 '92 h8/3834 u.m. fig. (syscr1) bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 lson 0 r/w 0 1 2 1 1 1 94 bits 6 to 4: standby timer select 2 to 0 (sts2 to sts0) these bits designate the time the cpu and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. the designation should be made according to the clock frequency so that the waiting time is at least 10 ms. bit 6 bit 5 bit 4 sts2 sts1 sts0 description 0 0 0 wait time = 8,192 states (initial value) 0 0 1 wait time = 16,384 states 0 1 0 wait time = 32,768 states 0 1 1 wait time = 65,536 states 1 * * wait time = 131,072 states note: * don? care bit 3: low speed on flag (lson) this bit chooses the system clock (? or subclock ( sub ) as the cpu operating clock when watch mode is cleared. the resulting operation mode depends on the combination of other control bits and interrupt input. bit 3 lson description 0 the cpu operates on the system clock (? (initial value) 1 the cpu operates on the subclock ( sub ) bits 2 to 0: reserved bits these bits are reserved; they are always read as 1, and cannot be modified. 2. system control register 2 (syscr2) syscr2 is an 8-bit read/write register for power-down mode control. upon reset, syscr2 is initialized to h'e0. h037 '92 h8/3834 u.m. fig. (syscr2) bit initial value read/write 7 1 6 1 5 1 4 nesel 0 r/w 3 dton 0 r/w 0 sa0 0 r/w 2 mson 0 r/w 1 sa1 0 r/w 95 bits 7 to 5: reserved bits these bits are reserved; they are always read as 1, and cannot be modified. bit 4: noise elimination sampling frequency select (nesel) this bit selects the frequency at which the watch clock signal ( w ) generated by the subclock pulse generator is sampled, in relation to the oscillator clock ( osc ) generated by the system clock pulse generator. when osc = 2 to 10 mhz, clear nesel to 0. bit 4 nesel description 0 sampling rate is osc /16 1 sampling rate is osc /4 bit 3: direct transfer on flag (dton) this bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a sleep instruction is executed. the mode to which the transition is made after the sleep instruction is executed depends on a combination of this and other control bits. bit 3 dton description 0 when a sleep instruction is executed in active mode, a transition (initial value) is made to standby mode, watch mode, or sleep mode when a sleep instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode 1 when a sleep instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if ssby = 0, mson = 1, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 when a sleep instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if ssby = 0, mson = 0, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 when a sleep instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 0, or to active (medium-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 1 96 bit 2: medium speed on flag (mson) after standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. bit 2 mson description 0 after standby, watch, or sleep mode is cleared, operation is in active (high-speed) mode when a sleep instruction is executed in active mode, a transition is made to sleep (high-speed) mode (initial value) 1 after standby, watch, or sleep mode is cleared, operation is in active (medium-speed) mode when a sleep instruction is executed in active mode, a transition is made to sleep (medium-speed) mode bits 1 and 0: subactive mode clock select (sa1 and sa0) these bits select the cpu clock rate ( w /2, w /4, or w /8) in subactive mode. sa1 and sa0 cannot be modified in subactive mode. bit 1 bit 0 sa1 sa0 description 0 0 w /8 (initial value) 0 1 w /4 1 * w /2 note: * don? care 97 5.2 sleep mode 5.2.1 transition to sleep mode 1. transition to sleep (high-speed) mode the system goes from active mode to sleep (high-speed) mode when a sleep instruction is executed while the ssby and lson bits in syscr1 and the mson and dton bits in syscr2 are all cleared to 0. in sleep (high-speed) mode cpu operation is halted but the on-chip peripheral functions other than pwm are operational. cpu register contents are retained. 2. transition to sleep (medium-speed) mode the system goes from active mode to sleep (medium-speed) mode when a sleep instruction is executed while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is set to 1, and the dton bit in syscr2 is cleared to 0. in sleep (medium-speed) mode, as in sleep (high-speed) mode, cpu operation is halted but the on-chip peripheral functions other than pwm are operational. the clock frequency in sleep (medium-speed) mode is 1/64 the frequency in sleep (high-speed) mode, however. cpu register contents are retained. 5.2.2 clearing sleep mode sleep mode is cleared by any interrupt (timer a, timer b1, timer b2, timer b3, timer c, timer e, timer x, timer y, timer v, irq 3 to irq 0 , int 7 to int 0 , nmi, sci2, sci1, or a/d converter) or by input at the res pin. sleep (medium-speed) mode is not cleared by an a/d converter interrupt, however. clearing by interrupt when an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. a transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep (medium-speed) mode to active (medium-speed) mode. sleep mode is not cleared if the i bit of the condition code register (ccr) is set to 1 or the particular interrupt is disabled in the interrupt enable register. clearing by res input when the res pin goes low, the cpu goes into the reset state and sleep mode is cleared. 5.2.3 clock frequency in sleep (medium-speed) mode operation in sleep (medium-speed) mode is clocked at 1/64 the frequency in sleep (high-speed) mode. 98 5.3 standby mode 5.3.1 transition to standby mode the system goes from active mode to standby mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, and bit tma3 in tma is cleared to 0. in standby mode the clock pulse generator stops, so the cpu and on-chip peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of cpu registers, on-chip ram, and some on-chip peripheral module registers are retained. on-chip ram contents will be further retained down to a minimum ram data retention voltage. the i/o ports go to the high-impedance state. 5.3.2 clearing standby mode standby mode is cleared by an interrupt (irq 1 , irq 0 , or nmi) or by input at the res pin. clearing by interrupt when an interrupt is requested, the system clock pulse generator starts. after the time set in bits sts2?ts0 in syscr1 has elapsed, a stable system clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. operation resumes in active (high- speed) mode if mson = 0 in syscr2, or active (medium-speed) mode if mson = 1. standby mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. clearing by res input when the res pin goes low, the system clock pulse generator starts and standby mode is cleared. after the pulse generator output has stabilized, if the res pin is driven high, the cpu starts reset exception handling. since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the res pin should be kept at the low level until the pulse generator output stabilizes. 99 5.3.3 oscillator settling time after standby mode is cleared bits sts2 to sts0 in syscr1 should be set as follows. when a crystal oscillator is used the table below gives settings for various operating frequencies. set bits sts2 to sts0 for a waiting time of at least 10 ms. when an external clock is used any values may be set. normally the minimum time (sts2 = sts1 = sts0 = 0) should be set. table 5-3 clock frequency and settling time (times are in ms) sts2 sts1 sts0 waiting time 5 mhz 4 mhz 2 mhz 1 mhz 0.5 mhz 0 0 0 8,192 states 1.6 2.0 4.1 8.2 0 0 1 16,384 states 3.2 4.1 8.2 32.8 0 1 0 32,768 states 6.6 8.2 32.8 65.5 0 1 1 65,536 states 32.8 65.5 131.1 1 * * 131,072 states 26.2 32.8 65.5 131.1 262.1 note: * don? care 16.4 13.1 16.4 16.4 16.4 100 5.4 watch mode 5.4.1 transition to watch mode the system goes from active or subactive mode to watch mode when a sleep instruction is executed while the ssby bit in syscr1 is set to 1 and bit tma3 in tma is set to 1. in watch mode, operation of on-chip peripheral modules other than timer a is halted. as long as a minimum required voltage is applied, the contents of cpu registers, the on-chip ram and some registers of the on-chip peripheral modules, are retained. i/o ports keep the same states as before the transition. 5.4.2 clearing watch mode watch mode is cleared by an interrupt (timer a, irq 0 , nmi) or by a low input at the res pin. clearing by interrupt when watch mode is cleared by a timer a interrupt or irq 0 interrupt, the mode to which a transition is made depends on the settings of lson in syscr1 and mson in syscr2. if both lson and mson are cleared to 0, transition is to active (high-speed) mode; if lson = 0 and mson = 1, transition is to active (medium-speed) mode; if lson = 1, transition is to subactive mode. when watch mode is cleared by an nmi interrupt request, the transition is to active (high- speed) mode if mson = 0 or to active (medium-speed) mode if mson = 1, but never to subactive mode. when the transition is to active mode, after the time set in syscr1 bits sts2?ts0 has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. watch mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. clearing by res input clearing by res pin is the same as for standby mode; see 5.3.2, clearing standby mode. 5.4.3 oscillator settling time after watch mode is cleared the waiting time is the same as for standby mode; see 5.3.3, oscillator settling time after standby mode is cleared. 101 5.5 subsleep mode 5.5.1 transition to subsleep mode the system goes from subactive mode to subsleep mode when a sleep instruction is executed while the ssby bit in syscr1 is cleared to 0, lson bit in syscr1 is set to 1, and tma3 bit in tma is set to 1. in subsleep mode, operation of on-chip peripheral modules other than timer a and timer c is halted. as long as a minimum required voltage is applied, the contents of cpu registers, the on-chip ram and some registers of the on-chip peripheral modules are retained. i/o ports keep the same states as before the transition. 5.5.2 clearing subsleep mode subsleep mode is cleared by an interrupt (timer a, timer c, nmi, irq 3 to irq 0 , int 7 to int 0 ) or by a low input at the res pin. clearing by interrupt when an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. subsleep mode is not cleared if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. clearing by res input clearing by res pin is the same as for standby mode; see 5.3.2, clearing standby mode. 102 5.6 subactive mode 5.6.1 transition to subactive mode subactive mode is entered from watch mode if a timer a, irq 0 , or nmi interrupt is requested while the lson bit in syscr1 is set to 1. from subsleep mode, subactive mode is entered if a timer a, timer c, nmi, irq 3 to irq 0 , or int 7 to int 0 interrupt is requested. a transition to subactive mode does not take place if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.6.2 clearing subactive mode subactive mode is cleared by a sleep instruction or by a low input at the res pin. clearing by sleep instruction if a sleep instruction is executed while the ssby bit in syscr1 is set to 1 and tma3 bit in tma is set to 1, subactive mode is cleared and watch mode is entered. if a sleep instruction is executed while ssby = 0 and lson = 1 in syscr1 and tma3 = 1 in tma, subsleep mode is entered. direct transfer to active mode is also possible; see 5.8, direct transfer, below. clearing by res pin clearing by res pin is the same as for standby mode; see 5.3.2, clearing standby mode. 5.6.3 operating frequency in subactive mode the operating frequency in subactive mode is set in bits sa1 and sa0 in syscr2. the choices are w /2, w /4, and w /8. 103 5.7 active (medium-speed) mode 5.7.1 transition to active (medium-speed) mode if the mson bit in syscr2 is set to 1 while the lson bit in syscr1 is cleared to 0, a transition to active (medium-speed) mode results from irq 0 , irq 1 , or nmi interrupts in standby mode, timer a, irq 0 , or nmi interrupts in watch mode, or any interrupt in sleep mode. a transition to active (medium-speed) mode does not take place if the i bit of ccr is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.7.2 clearing active (medium-speed) mode active (medium-speed) mode is cleared by a sleep instruction or by a low input at the res pin. clearing by sleep instruction a transition to standby mode takes place if the sleep instruction is executed while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is cleared to 0, and the tma3 bit in tma is cleared to 0. the system goes to watch mode if the ssby bit in syscr1 is set to 1 and bit tma3 in tma is set to 1 when a sleep instruction is executed. when both ssby and lson are cleared to 0 in syscr1 and a sleep instruction is executed, sleep (high-speed) mode is entered if mson is cleared to 0 in syscr2, and sleep (medium-speed) mode is entered if mson is set to 1. direct transfer to active (high-speed) mode or to subactive mode is also possible. see 5.8, direct transfer, below for details. clearing by res pin when the res pin goes low, the cpu enters the reset state and active (medium-speed) mode is cleared. 5.7.3 operating frequency in active (medium-speed) mode in active (medium-speed) mode, the cpu is clocked at 1/64 the frequency in active (high-speed) mode. 104 5.8 direct transfer the cpu can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. a direct transfer is a transition among these three modes without the stopping of program execution. a direct transfer can be made by executing a sleep instruction while the dton bit in syscr2 is set to 1. after the mode transition, direct transfer interrupt exception handling starts. if the direct transfer interrupt is disabled in interrupt enable register 2, a transition is made instead to sleep mode or watch mode. note that if a direct transition is attempted while the i bit in ccr is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting mode by means of an interrupt. direct transfer from active (high-speed) mode to active (medium-speed) mode when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is set to 1, and the dton bit in syscr2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode. direct transfer from active (medium-speed) mode to active (high-speed) mode when a sleep instruction is executed in active (medium-speed) mode while the ssby and lson bits in syscr1 are cleared to 0, the mson bit in syscr2 is cleared to 0, and the dton bit in syscr2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. direct transfer from active (high-speed) mode to subactive mode when a sleep instruction is executed in active (high-speed) mode while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made to subactive mode via watch mode. direct transfer from subactive mode to active (high-speed) mode when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is set to 1, the mson bit in syscr2 is cleared to 0, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in syscr1 bits sts2 to sts0 has elapsed. 105 direct transfer from active (medium-speed) mode to subactive mode when a sleep instruction is executed in active (medium-speed) while the ssby and lson bits in syscr1 are set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made to subactive mode via watch mode. direct transfer from subactive mode to active (medium-speed) mode when a sleep instruction is executed in subactive mode while the ssby bit in syscr1 is set to 1, the lson bit in syscr1 is set to 1, the mson bit in syscr2 is set to 1, the dton bit in syscr2 is set to 1, and the tma3 bit in tma is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in syscr1 bits sts2 to sts0 has elapsed. 106 section 6 rom 6.1 overview the h8/3927 has 60 kbytes of on-chip mask rom or prom. the h8/3926 has 48 kbytes of mask rom. the h8/3925 has 40 kbytes of mask rom. the h8/3924 has 32 kbytes of mask rom. the rom is connected to the cpu by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data. 6.1.1 block diagram figure 6-1 shows a block diagram of the on-chip rom. figure 6-1 rom block diagram (h8/3927) h'edfe h'edff internal data bus (upper 8 bits) internal data bus (lower 8 bits) even-numbered address odd-numbered address h'edfe h'0002 h'0000 h'0000 h'0002 h'0001 h'0003 on-chip rom 107 6.2 prom mode 6.2.1 setting to prom mode if the on-chip rom is prom, setting the chip to prom mode stops operation as a microcontroller and allows the prom to be programmed in the same way as the standard hn27c101 eprom. page programming is not supported, however. table 6-1 shows how to set the chip to prom mode. table 6-1 setting to prom mode pin name setting test high level pb 4 /an 4 low level pb 5 /an 5 pb 6 /an 6 high level 6.2.2 socket adapter pin arrangement and memory map a standard prom programmer can be used to program the prom. a socket adapter is required for conversion to 32 pins, as listed in table 6-2. figure 6-2 shows the pin-to-pin wiring of the socket adapter. figure 6-3 shows a memory map. table 6-2 socket adapter package socket adapter 80-pin (fp-80b) hs3927esf01h 80-pin (tfp-80f) hs3927esn01h * note: * under development 108 figure 6-2 socket adapter pin correspondence (with hn27c101) h8/3927 eprom socket res p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 p7 0 nmi p7 2 p7 3 p7 4 p7 5 p7 6 p1 4 p1 5 p7 7 p7 1 p1 3 av cc test x 1 pb 6 p1 1 p1 2 p1 6 v ss av ss pb 4 pb 5 hn27c101 (32-pin) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 16 12 31 32 33 34 35 36 37 38 54 53 52 51 50 49 48 47 39 13 41 42 43 44 45 68 69 46 40 67 63 72 6 8 78 65 66 70 9 5 80 79 pin v pp eo 0 eo 1 eo 2 eo 3 eo 4 eo 5 eo 6 eo 7 ea 0 ea 1 ea 2 ea 3 ea 4 ea 5 ea 6 ea 7 ea 8 ea 9 ea 10 ea 11 ea 12 ea 13 ea 14 ea 15 ea 16 ce oe pgm v cc v ss note: pins not indicated in the figure should be left open. 10 29 30 31 32 33 34 35 36 52 51 50 49 48 47 46 45 37 11 39 40 41 42 43 66 67 44 38 65 61 70 4 6 76 63 64 68 7 3 78 77 v cc pin tfp-80f fp-80b 109 figure 6-3 h8/3927 memory map in prom mode on-chip prom missing area h'0000 h'edff h'0000 h'edff h'1ffff address in mcu mode address in prom mode * note: * if read in prom mode, this address area returns unpredictable output data. when programming with a prom programmer, be sure to specify addresses from h'0000 to h'edff. if address h'ee00 and higher addresses are programmed by mistake, it may become impossible to program the prom or verify the programmed data. when programming, assign h'ff data to this address area (h'ee00 to h'1ffff). 110 6.3 programming the write, verify, and other modes are selected as shown in table 6-3 in prom mode. table 6-3 mode selection in prom mode pin mode ce oe pgm v pp v cc eo 7 to eo 0 ea 16 to ea 0 write l h l v pp v cc data input address input verify l l h v pp v cc data output address input programming l l l v pp v cc high impedance address input disabled l h h h l l h h h notation l: low level h: high level v pp : v pp level v cc : v cc level the specifications for writing and reading the on-chip prom are identical to those for the standard hn27c101 eprom. page programming is not supported, however. the prom writer must not be set to page mode. a prom programmer that provides only page programming mode cannot be used. when selecting a prom programer, check that it supports a byte-by-byte high-speed, high- reliability programming method. be sure to set the address range to h'0000 to h'edff. 6.3.1 writing and verifying an efficient, high-speed, high-reliability method is available for writing and verifying the prom data. this method achieves high speed without voltage stress on the device and without lowering the reliability of written data. the basic flow of this high-speed, high-reliability programming method is shown in figure 6-4. 111 figure 6-4 high-speed, high-reliability programming flow chart start set write/verify mode v = 6.0 v ?0.25 v, v = 12.5 v ?0.3 v cc pp address = 0 n = 0 n + 1 n ? pw verify write time t = 0.2n ms opw last address? set read mode v = 5.0 v ?0.25 v, v = v cc pp cc read all addresses? end error n 25 < address + 1 address ? no yes no yes yes no no go go write time t = 0.2 ms ?5% 112 table 6-4 and table 6-5 give the electrical characteristics in programming mode. table 6-4 dc characteristics (conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, t a = 25? 5?) test item symbol min typ max unit condition input high- eo 7 to eo 0 , ea 16 to ea 0 v ih 2.4 v cc + 0.3 v level voltage oe , ce , pgm input low- eo 7 to eo 0 , ea 16 to ea 0 v il ?.3 0.8 v level voltage oe , ce , pgm output high- eo 7 to eo 0 v oh 2.4 v i oh = ?00 a level voltage output low- eo 7 to eo 0 v ol 0.45 v i ol = 0.8 ma level voltage input leakage eo 7 to eo 0 , ea 16 to ea 0 |i li | 2 a v in = 5.25 v/ current oe , ce , pgm 0.5 v v cc current i cc 40 ma v pp current i pp 40 ma 113 table 6-5 ac characteristics (conditions: v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, t a = 25? 5?) test item symbol min typ max unit condition address setup time t as 2 s figure 6-5 * 1 oe setup time t oes 2 s data setup time t ds 2 s address hold time t ah 0 s data hold time t dh 2 s data output disable time t df * 2 130 ns v pp setup time t vps 2 s programming pulse width t pw 0.19 0.20 0.21 ms pgm pulse width for overwrite t opw * 3 0.19 5.25 ms programming v cc setup time t vcs 2 s ce setup time t ces 2 s data output delay time t oe 0 200 ns notes: 1. input pulse level: 0.45 v to 2.4 v input rise time/fall time 20 ns timing reference levels input: 0.8 v, 2.0 v output: 0.8 v, 2.0 v 2. t df is defined at the point at which the output is floating and the output level cannot be read. 3. t opw is defined by the value given in figure 6-4, high-speed, high-reliability programming flow chart. 114 figure 6-5 shows a write/verify timing diagram. figure 6-5 prom write/verify timing address data v pp v cc ce pgm oe v pp v cc v cc v cc write verify input data output data t as t ds t vps t vcs t ces t pw t opw * t dh t oes t oe t df t ah note: * t is defined by the value given in figure 6-4, high-speed, high-reliability programming flow chart. opw +1 115 6.3.2 programming precautions use the specified programming voltage and timing. the programming voltage in prom mode (v pp ) is 12.5 v. use of a higher voltage can permanently damage the chip. be especially careful with respect to prom programmer overshoot. setting the prom programmer to hitachi specifications for the hn27c101 will result in correct v pp of 12.5 v. make sure the index marks on the prom programmer socket, socket adapter, and chip are properly aligned. if they are not, the chip may be destroyed by excessive current flow. before programming, be sure that the chip is properly mounted in the prom programmer. avoid touching the socket adapter or chip while programming, since this may cause contact faults and write errors. select the programming mode carefully. the chip cannot be programmed in page programming mode. when programming with a prom programmer, be sure to specify addresses from h'0000 to h'edff. if address h'ee00 and higher addresses are programmed by mistake, it may become impossible to program the prom or verify the programmed data. when programming, assign h'ff data to the address area from h'ee00 to h'1ffff. 116 6.4 reliability of programmed data a highly effective way of assuring data retention characteristics after programming is to screen the chips by baking them at a temperature of 150?. this quickly eliminates prom memory cells prone to initial data retention failure. figure 6-6 shows a flowchart of this screening procedure. figure 6-6 recommended screening procedure if write errors occur repeatedly while the same prom programmer is being used, stop programming and check for problems in the prom programmer and socket adapter, etc. please notify your hitachi representative of any problems occurring during programming or in screening after high-temperature baking. h8/300l '91 fig. 4-6 install write program and verify contents bake at high temperature with power off 125? to 150?, 24 hrs to 48 hrs read and check program 117 section 7 ram 7.1 overview the h8/3927 series has 1 kbyte of high-speed static ram on-chip. the ram is connected to the cpu by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 block diagram figure 7-1 shows a block diagram of the on-chip ram. figure 7-1 ram block diagram h'ff7e h'ff7f internal data bus (upper 8 bits) internal data bus (lower 8 bits) even-numbered address odd-numbered address h'ff7e h'fb82 h'fb80 h'fb80 h'fb82 h'fb81 h'fb83 on-chip ram 119 section 8 i/o ports 8.1 overview the h8/3927 series is provided with seven 8-bit i/o ports, one 8-bit input-only port, one 4-bit input-only port. table 8-1 indicates the functions of each port. each port has of a port control register (pcr) that controls input and output, and a port data register (pdr) for storing output data. input or output can be assigned to individual bits. see 2.9.2, notes on bit manipulation, for information on executing bit-manipulation instructions to write data in pcr or pdr. block diagrams of each port are given in appendix c. table 8-1 port functions function switching port description pins other functions register port 1 8-bit i/o port p1 7 /irq 3 /trgv external interrupt 3, timer v trigger pmr1 input pull-up p1 6 to p1 5 / input option irq 2 to irq 1 external interrupts 2 and 1 p1 4 /pwm 14-bit pwm output pmr1 p1 3 /tmic timer c event input p1 2 /ud timer c count-up/down select p1 1 /tmoe timer e output pmr1 p1 0 /tmow timer a clock output pmr1 port 3 8-bit i/o port p3 7 / cs sci2 chip select input ( cs ), strobe pmr3 input pull-up p3 6 /strb output (strb), data output (so 2 ), option p3 5 /so 2 data input (si 2 ), and clock input/ high-current port p3 4 /si 2 output (sck 2 ) p3 3 /sck 2 p3 2 /so 1 sci1 data output (so 1 ), data input pmr3 p3 1 /si 1 (si 1 ), clock input/output (sck 1 ) p3 0 /sck 1 port 4 8-bit i/o port p4 7 to p4 0 port 5 8-bit i/o port p5 7 to int 7 / int interrupt 7 input pull-up tmiy timer y event input p5 6 to int 6 / int interrupt 6 tmib timer b event input p5 5 to int 5 / int interrupt 5 adtrg a/d converter external trigger input p5 4 to p5 0 / int interrupts 4 to 0 int 4 to int 0 121 table 8-1 port functions (cont) function switching port description pins other functions register port 6 8-bit i/o port p6 7 to p6 0 / realtime output port 7 to 0 rter rp 7 to rp 0 port 7 8-bit i/o port p7 7 p7 6 /tmov timer v compare-match output tcsrv p7 5 /tmciv timer v clock input p7 4 /tmriv timer v reset input p7 3 to p7 0 port 8 8-bit i/o port p8 7 p8 6 /ftid timer x input capture d input p8 5 /ftic timer x input capture c input p8 4 /ftib timer x input capture b input p8 3 /ftia timer x input capture a input p8 2 /ftob timer x output compare b output tocr p8 1 /ftoa timer x output compare a output tocr p8 0 /ftci timer x clock input port b 8-bit input port pb 7 to pb 0 / a/d converter analog input an 7 to an 0 (an 7 to an 0 ) port c 4-bit input port pc 3 to pc 0 / d/a converter analog output da 3 to da 0 (da 3 to da 0 ) 122 8.2 port 1 8.2.1 overview port 1 is an 8-bit i/o port. figure 8-1 shows its pin configuration. figure 8-1 port 1 pin configuration 8.2.2 register configuration and description table 8-2 shows the port 1 register configuration. table 8-2 port 1 registers name abbrev. r/w initial value address port data register 1 pdr1 r/w h'00 h'ffd4 port control register 1 pcr1 w h'00 h'ffe4 port pull-up control register 1 pucr1 r/w h'00 h'ffed port mode register 1 pmr1 r/w h'00 h'fffc p1 /irq /trgv p1 /irq p1 /irq p1 /pwm p1 /tmic p1 /ud p1 /tmoe p1 /tmow 7 6 5 4 3 2 1 0 3 2 1 port 1 123 1. port data register 1 (pdr1) pdr1 is an 8-bit register that stores data for pins p1 7 through p1 0 . if port 1 is read while pcr1 bits are set to 1, the values stored in pdr1 are read, regardless of the actual pin states. if port 1 is read while pcr1 bits are cleared to 0, the pin states are read. upon reset, pdr1 is initialized to h'00. 2. port control register 1 (pcr1) pcr1 is an 8-bit register for controlling whether each of the port 1 pins p1 7 to p1 0 functions as an input pin or output pin. setting a pcr1 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr1 and in pdr1 are valid only when the corresponding pin is designated in pmr1 as a general i/o pin. upon reset, pcr1 is initialized to h'00. pcr1 is a write-only register, which is always read as all 1s. 3. port pull-up control register 1 (pucr1) pucr1 controls whether the mos pull-up of each port 1 pin is on or off. when a pcr1 bit is cleared to 0, setting the corresponding pucr1 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr1 is initialized to h'00. h037 '92 h8/3834 u.m. pucr1 bit initial value read/write 7 pucr1 0 r/w 6 pucr1 0 r/w 5 pucr1 0 r/w 4 pucr1 0 r/w 3 pucr1 0 r/w 0 pucr1 0 r/w 2 pucr1 0 r/w 1 pucr1 0 r/w 7 6 5 4 3 2 1 0 h037 '92 h8/3834 u.m. pcr1 bit initial value read/write 7 pcr1 0 w 6 pcr1 0 w 5 pcr1 0 w 4 pcr1 0 w 3 pcr1 0 w 0 pcr1 0 w 2 pcr1 0 w 1 pcr1 0 w 7 6 5 4 3 2 1 0 h037 '92 h8/3834 u.m. pdrb bit initial value read/write 7 p1 0 r/w 6 p1 0 r/w 5 p1 0 r/w 4 p1 0 r/w 3 p1 0 r/w 0 p1 0 r/w 2 p1 0 r/w 1 p1 0 r/w 7 6 5 4 3 2 1 0 124 4. port mode register 1 (pmr1) pmr1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. upon reset, pmr1 is initialized to h'04. bit 7: p1 7 /irq 3 /trgv pin function switch (irq3) this bit selects whether pin p1 7 /irq 3 /trgv is used as p1 7 or as irq 3 /trgv. bit 7 irq3 description 0 functions as p1 7 i/o pin (initial value) 1 functions as irq 3 /trgv input pin note: rising or falling edge sensing can be designated for irq 3 . rising, falling, or both edge sensing can be designated for trgv. for details on trgv settings, see 9.8.2 (5), timer control register v1 (tcrv1). bit 6: p1 6 /irq 2 pin function switch (irq2) this bit selects whether pin p1 6 /irq 2 is used as p1 6 or as irq 2 . bit 6 irq2 description 0 functions as p1 6 i/o pin (initial value) 1 functions as irq 2 input pin note: rising or falling edge sensing can be designated for irq 2 . bit 5: p1 5 /irq 1 pin function switch (irq1) this bit selects whether pin p1 5 /irq 1 is used as p1 5 or as irq 1 . bit 5 irq1 description 0 functions as p1 5 i/o pin (initial value) 1 functions as irq 1 input pin note: rising or falling edge sensing can be designated for irq 1 . bit initial value read/write 7 irq3 0 r/w 6 irq2 0 r/w 5 irq1 0 r/w 4 pwm 0 r/w 3 tciceg 0 r/w 0 tmow 0 r/w 2 ? 1 1 tmoe 0 r/w 125 bit 4: p1 4 /pwm pin function switch (pwm) this bit selects whether pin p1 4 /pwm is used as p1 4 or as pwm. bit 4 pwm description 0 functions as p1 4 i/o pin (initial value) 1 functions as pwm output pin bit 3: tmic edge select (tciceg) this bit selects the input sensing of the tmic pin. bit 3 tciceg description 0 the falling edge of tmic pin input is detected (initial value) 1 the rising edge of tmic pin input is detected bit 2: reserved bit bit 2 is reserved; it is always read as 1, and cannot be modified. bit 1: p1 1 /tmoe pin function switch (tmoe) this bit selects whether pin p1 1 /tmoe is used as p1 1 or as tmoe. bit 1 tmoe description 0 functions as p1 1 i/o pin (initial value) 1 functions as tmoe output pin bit 0: p1 0 /tmow pin function switch (tmow) this bit selects whether pin p1 0 /tmow is used as p1 0 or as tmow. bit 0 tmow description 0 functions as p1 0 i/o pin (initial value) 1 functions as tmow output pin 126 8.2.3 pin functions table 8-3 shows the port 1 pin functions. table 8-3 port 1 pin functions pin pin functions and selection method p1 7 /irq 3 /trgv the pin function depends on bit irq3 in pmr1 and bit pcr1 7 in pcr1. irq3 0 1 pcr1 7 0 1 * pin function p1 7 input pin p1 7 output pin irq 3 /trgv input pin p1 6 /irq 2 / the pin function depends on bits irq2 and irq1 in pmr1 and bit pcr1 n in pcr1. p1 5 /irq 1 (m = n ?4, n = 6, 5) irqm 0 1 pcr1 n 0 1 * pin function p1 n input pin p1 n output pin irq m input pin p1 4 /pwm the pin function depends on bit pwm in pmr1 and bit pcr1 4 in pcr1. pwm 0 1 pcr1 4 0 1 * pin function p1 4 input pin p1 4 output pin pwm output pin p1 3 /tmic the pin function depends on bit pcr1 3 in pcr1. pcr1 3 0 1 pin function p1 3 input pin p1 3 output pin tmic input pin p1 2 /ud the pin function depends on bit pcr1 2 in pcr1. pcr1 2 0 1 pin function p1 2 input pin p1 2 output pin ud input pin note: * don? care 127 table 8-3 port 1 pin functions (cont) pin pin functions and selection method p1 1 /tmoe the pin function depends on bit tmoe in pmr1 and bit pcr1 1 in pcr1. tmofl 0 1 pcr1 1 0 1 * pin function p1 1 input pin p1 1 output pin tmoe output pin p1 0 /tmow the pin function depends on bit tmow in pmr1 and bit pcr1 0 in pcr1. tmow 0 1 pcr1 0 0 1 * pin function p1 0 input pin p1 0 output pin tmow output pin note: * don? care 8.2.4 pin states table 8-4 shows the port 1 pin states in each operating mode. table 8-4 port 1 pin states pins reset sleep subsleep standby watch subactive active p1 7 /irq 3 /trgv high- retains retains high- retains functional functional p1 6 /irq 2 impedance previous previous impedance * previous p1 5 /irq 1 state state state p1 4 /pwm p1 3 /tmic p1 2 /ud p1 1 /tmoe p1 0 /tmow note: * a high-level signal is output when the mos pull-up is in the on state. 8.2.5 mos input pull-up port 1 has a built-in mos input pull-up function that can be controlled by software. when a pcr1 bit is cleared to 0, setting the corresponding pucr1 bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a reset. pcr1 n 0 1 pucr1 n 0 1 * mos input pull-up off on off note: * don? care n = 7 to 0 128 8.3 port 3 8.3.1 overview port 3 is an 8-bit i/o port, configured as shown in figure 8-2. figure 8-2 port 3 pin configuration 8.3.2 register configuration and description table 8-5 shows the port 3 register configuration. table 8-5 port 3 registers name abbrev. r/w initial value address port data register 3 pdr3 r/w h'00 h'ffd6 port control register 3 pcr3 w h'00 h'ffe6 port pull-up control register 3 pucr3 r/w h'00 h'ffee port mode register 3 pmr3 r/w h'00 h'fffd port mode register 7 pmr7 r/w h'fc h'ffff h8/3834 '92 fig. 8-3 p3 /cs p3 /strb p3 /so p3 /si p3 /sck p3 /so p3 /si p3 /sck 7 6 5 4 3 2 1 0 2 port 3 1 1 1 2 2 129 1. port data register 3 (pdr3) pdr3 is an 8-bit register that stores data for port 3 pins p3 7 to p3 0 . if port 3 is read while pcr3 bits are set to 1, the values stored in pdr3 are read, regardless of the actual pin states. if port 3 is read while pcr3 bits are cleared to 0, the pin states are read. upon reset, pdr3 is initialized to h'00. 2. port control register 3 (pcr3) pcr3 is an 8-bit register for controlling whether each of the port 3 pins p3 7 to p3 0 functions as an input pin or output pin. setting a pcr3 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. the settings in pcr3 and in pdr3 are valid only when the corresponding pin is designated in pmr3 as a general i/o pin. upon reset, pcr3 is initialized to h'00. pcr3 is a write-only register, which is always read as all 1s. 3. port pull-up control register 3 (pucr3) pucr3 controls whether the mos pull-up of each port 3 pin is on or off. when a pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr3 is initialized to h'00. h037 '92 h8/3834 u.m. pucr3 bit initial value read/write 7 pucr3 0 r/w 6 pucr3 0 r/w 5 pucr3 0 r/w 4 pucr3 0 r/w 3 pucr3 0 r/w 0 pucr3 0 r/w 2 pucr3 0 r/w 1 pucr3 0 r/w 7 6 5 4 3 2 1 0 h037 '92 h8/3834 u.m. pcr3 bit initial value read/write 7 pcr3 0 w 6 pcr3 0 w 5 pcr3 0 w 4 pcr3 0 w 3 pcr3 0 w 0 pcr3 0 w 2 pcr3 0 w 1 pcr3 0 w 7 6 5 4 3 2 1 0 h037 '92 h8/3834 u.m. pdr3 bit initial value read/write 7 p3 0 r/w 6 p3 0 r/w 5 p3 0 r/w 4 p3 0 r/w 3 p3 0 r/w 0 p3 0 r/w 2 p3 0 r/w 1 p3 0 r/w 7 6 5 4 3 2 1 0 130 4. port mode register 3 (pmr3) pmr3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. upon reset, pmr3 is initialized to h'00. bit 7: p3 7 / cs pin function switch (cs) this bit selects whether pin p3 7 / cs is used as p3 7 or as cs . bit 7 cs description 0 functions as p3 7 i/o pin (initial value) 1 functions as cs input pin bit 6: p3 6 /strb pin function switch (strb) this bit selects whether pin p3 6 /strb is used as p3 6 or as strb. bit 6 strb description 0 functions as p3 6 i/o pin (initial value) 1 functions as strb output pin bit 5: p3 5 /so 2 pin function switch (so2) this bit selects whether pin p3 5 /so 2 is used as p3 5 or as so 2 . bit 5 so2 description 0 functions as p3 5 i/o pin (initial value) 1 functions as so 2 output pin h037 '92 h8/3834 u.m. pmr3 bit initial value read/write 7 cs 0 r/w 6 strb 0 r/w 5 so2 0 r/w 4 si2 0 r/w 3 sck2 0 r/w 0 sck1 0 r/w 2 so1 0 r/w 1 si1 0 r/w 131 bit 4: p3 4 /si 2 pin function switch (si2) this bit selects whether pin p3 4 /si 2 is used as p3 4 or as si 2 . bit 4 si2 description 0 functions as p3 4 i/o pin (initial value) 1 functions as si 2 input pin bit 3: p3 3 /sck 2 pin function switch (sck2) this bit selects whether pin p3 3 /sck 2 is used as p3 3 or as sck 2 . bit 3 sck2 description 0 functions as p3 3 i/o pin (initial value) 1 functions as sck 2 i/o pin bit 2: p3 2 /so 1 pin function switch (so1) this bit selects whether pin p3 2 /so 1 is used as p3 2 or as so 1 . bit 2 so1 description 0 functions as p3 2 i/o pin (initial value) 1 functions as so 1 output pin bit 1: p3 1 /si 1 pin function switch (si1) this bit selects whether pin p3 1 /si 1 is used as p3 1 or as si 1 . bit 1 si1 description 0 functions as p3 1 i/o pin (initial value) 1 functions as si 1 input pin bit 0: p3 0 /sck 1 pin function switch (sck1) this bit selects whether pin p3 0 /sck 1 is used as p3 0 or as sck 1 . bit 0 sck1 description 0 functions as p3 0 i/o pin (initial value) 1 functions as sck 1 i/o pin 132 5. port mode register 7 (pmr7) pmr7 is an 8-bit read/write register that turns the pmos transistors of pins p3 5 /so 2 and p3 2 /so 1 on and off. upon reset, pmr7 is initialized to h'fc. bits 7 to 2: reserved bits bits 7 to 2 are reserved; they are always read as 1, and cannot be modified. bit 1: p3 5 /so 2 pin pmos control (pof2) this bit controls the pmos transistor in the p3 5 /so 2 pin output buffer. bit 1 pof2 description 0 cmos output (initial value) 1 nmos open-drain output bit 0: p3 2 /so 1 pin pmos control (pof1) this bit controls the pmos transistor in the p3 2 /so 1 pin output buffer. bit 0 pof1 description 0 cmos output (initial value) 1 nmos open-drain output bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 4 ? 1 3 ? 1 0 pof1 0 r/w 2 ? 1 1 pof2 0 r/w 133 8.3.3 pin functions table 8-6 shows the port 3 pin functions. table 8-6 port 3 pin functions pin pin functions and selection method p3 7 / cs the pin function depends on bit cs in pmr3 and bit pcr3 7 in pcr3. cs 0 1 pcr3 7 0 1 * pin function p3 7 input pin p3 7 output pin cs input pin p3 6 /strb the pin function depends on bit strb in pmr3 and bit pcr3 6 in pcr3. strb 0 1 pcr3 6 0 1 * pin function p3 6 input pin p3 6 output pin strb output pin p3 5 /so 2 the pin function depends on bit so2 in pmr3 and bit pcr3 5 in pcr3. so2 0 1 pcr3 5 0 1 * pin function p3 5 input pin p3 5 output pin so 2 output pin p3 4 /si 2 the pin function depends on bit si2 in pmr3 and bit pcr3 4 in pcr3. si2 0 1 pcr3 4 0 1 * pin function p3 4 input pin p3 4 output pin si 2 input pin p3 3 /sck 2 the pin function depends on bit sck2 in pmr3, bits cks2 to cks0 in scr2, and bit pcr3 3 in pcr3. sck2 0 1 cks2 to cks0 * not 111 111 pcr3 3 0 1 * * pin function p3 3 input pin p3 3 output pin sck 2 output pin sck 2 input pin note: * don? care 134 table 8-6 port 3 pin functions (cont) pin pin functions and selection method p3 2 /so 1 the pin function depends on bit so1 in pmr3 and bit pcr3 2 in pcr3. so1 0 1 pcr3 2 0 1 * pin function p3 2 input pin p3 2 output pin so 1 output pin p3 1 /si 1 the pin function depends on bit si1 in pmr3 and bit pcr3 1 in pcr3. si1 0 1 pcr3 1 0 1 * pin function p3 1 input pin p3 1 output pin si 1 input pin p3 0 /sck 1 the pin function depends on bit sck1 in pmr3, bit cks3 in scr1, and bit pcr3 0 in pcr3. sck1 0 1 cks3 * 0 1 pcr3 0 0 1 * * pin function p3 0 input pin p3 0 output pin sck 1 output pin sck 1 input pin note: * don? care 135 8.3.4 pin states table 8-7 shows the port 3 pin states in each operating mode. table 8-7 port 3 pin states pins reset sleep subsleep standby watch subactive active p3 7 / cs high- retains retains high- retains functional functional p3 6 /strb impedance previous previous impedance * previous p3 5 /so 2 state state state p3 4 /si 2 p3 3 /sck 2 p3 2 /so 1 p3 1 /si 1 p3 0 /sck 1 note: * a high-level signal is output when the mos pull-up is in the on state. 8.3.5 mos input pull-up port 3 has a built-in mos input pull-up function that can be controlled by software. when a pcr3 bit is cleared to 0, setting the corresponding pucr3 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr3 n 0 1 pucr3 n 0 1 * mos input pull-up off on off note: * don? care (n = 7 to 0) 136 8.4 port 4 8.4.1 overview port 4 is an 8-bit i/o port, configured as shown in figure 8-3. figure 8-3 port 4 pin configuration 8.4.2 register configuration and description table 8-8 shows the port 4 register configuration. table 8-8 port 4 registers name abbrev. r/w initial value address port data register 4 pdr4 r/w h'00 h'ffd7 port control register 4 pcr4 w h'00 h'ffe7 1. port data register 4 (pdr4) pdr4 is an 8-bit register that stores data for port 4 pins p4 7 to p4 0 . if port 4 is read while pcr4 bits are set to 1, the values stored in pdr4 are read, regardless of the actual pin states. if port 4 is read while pcr4 bits are cleared to 0, the pin states are read. upon reset, pdr4 is initialized to h'00. bit initial value read/write 7 p4 7 0 r/w 6 p4 6 0 r/w 5 p4 5 0 r/w 4 p4 4 0 r/w 3 p4 0 r/w 0 p4 0 r/w 2 p4 0 r/w 1 p4 0 r/w 3 2 1 0 p4 p4 p4 p4 p4 p4 p4 p4 7 6 5 4 3 2 1 0 port 4 137 2. port control register 4 (pcr4) pcr4 controls whether each of the port 4 pins p4 7 to p4 0 functions as an input pin or output pin. setting a pcr4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. upon reset, pcr4 is initialized to h'00. pcr4 is a write-only register, which is always reads as all 1s. 8.4.3 pin functions table 8-9 shows the port 4 pin functions. table 8-9 port 4 pin functions pin pin functions and selection method p4 n the pin function depends on bit pcr4 n in pcr4. (n = 7 to 0) pcr4 n 0 1 pin function p4 n input pin p4 n output pin 8.4.4 pin states table 8-10 shows the port 4 pin states in each operating mode. table 8-10 port 4 pin states pins reset sleep subsleep standby watch subactive active p4 7 to p4 0 high- retains retains high- retains functional functional impedance previous previous impedance previous state state state bit initial value read/write 7 pcr4 7 0 w 6 pcr4 6 0 w 5 pcr4 5 0 w 4 pcr4 4 0 w 3 pcr4 3 0 w 0 pcr4 0 w 2 pcr4 0 w 1 pcr4 0 w 2 1 0 138 8.5 port 5 8.5.1 overview port 5 is an 8-bit i/o port, configured as shown in figure 8-4. figure 8-4 port 5 pin configuration 8.5.2 register configuration and description table 8-11 shows the port 5 register configuration. table 8-11 port 5 registers name abbrev. r/w initial value address port data register 5 pdr5 r/w h'00 h'ffd8 port control register 5 pcr5 w h'00 h'ffe8 port pull-up control register 5 pucr5 r/w h'00 h'ffef p5 7 /int 7 /tmiy p5 6 /int 6 /tmib p5 5 /int 5 /adtrg p5 4 /int 4 p5 3 /int 3 p5 2 /int 2 p5 1 /int 1 p5 0 /int 0 port 5 139 1. port data register 5 (pdr5) pdr5 is an 8-bit register that stores data for port 5 pins p5 7 to p5 0 . if port 5 is read while pcr5 bits are set to 1, the values stored in pdr5 are read, regardless of the actual pin states. if port 5 is read while pcr5 bits are cleared to 0, the pin states are read. upon reset, pdr5 is initialized to h'00. 2. port control register 5 (pcr5) pcr5 is an 8-bit register for controlling whether each of the port 5 pins p5 7 to p5 0 functions as an input pin or output pin. setting a pcr5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. upon reset, pcr5 is initialized to h'00. pcr5 is a write-only register, which is always read as all 1s. 3. port pull-up control register 5 (pucr5) pucr5 controls whether the mos pull-up of each port 5 pin is on or off. when a pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the mos pull-up for the corresponding pin, while clearing the bit to 0 turns off the mos pull-up. upon reset, pucr5 is initialized to h'00. h037 '92 h8/3834 u.m. pucr5 bit initial value read/write 7 pucr5 0 r/w 6 pucr5 0 r/w 5 pucr5 0 r/w 4 pucr5 0 r/w 3 pucr5 0 r/w 0 pucr5 0 r/w 2 pucr5 0 r/w 1 pucr5 0 r/w 7 6 5 4 3 2 1 0 h037 '92 h8/3834 u.m. pcr5 bit initial value read/write 7 pcr5 0 w 6 pcr5 0 w 5 pcr5 0 w 4 pcr5 0 w 3 pcr5 0 w 0 pcr5 0 w 2 pcr5 0 w 1 pcr5 0 w 7 6 5 4 3 2 1 0 h037 '92 h8/3834 u.m. pdr5 bit initial value read/write 7 p5 0 r/w 6 p5 0 r/w 5 p5 0 r/w 4 p5 0 r/w 3 p5 0 r/w 0 p5 0 r/w 2 p5 0 r/w 1 p5 0 r/w 7 6 5 4 3 2 1 0 140 8.5.3 pin functions table 8-12 shows the port 5 pin functions. table 8-12 port 5 pin functions pin pin functions and selection method p5 7 /int 7 /tmiy the pin function depends on bit pcr5 7 in pcr5. pcr5 7 0 1 pin function p5 7 input pin p5 7 output pin int 7 input pin and tmiy input pin p5 6 /int 6 /tmib the pin function depends on bit pcr5 6 in pcr5. pcr5 6 0 1 pin function p5 6 input pin p5 6 output pin int 6 input pin and tmib input pin p5 5 /int 5 / the pin function depends on bit pcr5 5 in pcr5. adtrg pcr5 5 0 1 pin function p5 5 input pin p5 5 output pin int 5 input pin and adtrg input pin p5 4 /int 4 to the pin function depends on bit pcr5 n in pcr5. p5 0 /int 0 (n = 4 to 0) pcr5 n 0 1 pin function p5 n input pin p5 n output pin int n input pin 141 8.5.4 pin states table 8-13 shows the port 5 pin states in each operating mode. table 8-13 port 5 pin states pins reset sleep subsleep standby watch subactive active p5 7 /int 7 / high- retains retains high- retains functional functional tmiy to impedance previous previous impedance * previous p5 0 /int 0 state state state note: * a high-level signal is output when the mos pull-up is in the on state. 8.5.5 mos input pull-up port 5 has a built-in mos input pull-up function that can be controlled by software. when a pcr5 bit is cleared to 0, setting the corresponding pucr5 bit to 1 turns on the mos pull-up for that pin. the mos pull-up function is in the off state after a reset. pcr5 n 0 1 pucr5 n 0 1 * mos input pull-up off on off note: * don? care (n = 7 to 0) 142 8.6 port 6 8.6.1 overview port 6 is an 8-bit i/o port that also provides a realtime output function. figure 8-5 shows its pin configuration. the realtime output function enables output data or the input/output direction to be changed instantly by an external trigger input. figure 8-5 port 6 pin configuration 8.6.2 register configuration and description table 8-14 shows the port 6 register configuration. table 8-14 port 6 registers name abbrev. r/w initial value address port data register 6 pdr6 r/w h'00 h'ffd9 port control register 6 pcr6 w h'00 h'ffe9 realtime enable register rter r/w h'00 h'fffe port data register slave pdrs h'00 port control register slave pcrs h'00 p6 7 /rp 7 p6 6 /rp 6 p6 5 /rp 5 p6 4 /rp 4 p6 3 /rp 3 p6 2 /rp 2 p6 1 /rp 1 p6 0 /rp 0 port 6 143 1. port data register 6 (pdr6) pdr6 is an 8-bit register that stores data for port 6 pins p6 7 to p6 0 . upon reset, pdr6 is initialized to h'00. 2. port control register 6 (pcr6) pcr6 is an 8-bit register for controlling whether each of the port 6 pins p6 7 to p6 0 functions as an input pin or output pin. upon reset, pcr6 is initialized to h'00. pcr6 is a write-only register, which always reads all 1s. 3. realtime enable register (rter) rter is an 8-bit read/write register, controlling the selection of pin functions for port 6 pins p6 7 /rp 7 to p6 0 /rp 0 . setting an rter bit to 1 makes the corresponding pin a realtime port (rp) output pin, while clearing the bit to 0 makes the pin an ordinary port (p6) pin. if port 6 is read while rter bits are set to 1, the values stored in pdr6 are read, regardless of the actual pin states. upon reset, rter is initialized to h'00. bit initial value read/write 7 rter 7 0 r/w 6 rter 6 0 r/w 5 rter 5 0 r/w 4 rter 4 0 r/w 3 rter 3 0 r/w 0 rter 0 0 r/w 2 rter 2 0 r/w 1 rter 1 0 r/w bit initial value read/write 7 pcr6 7 0 r/w 6 pcr6 6 0 r/w 5 pcr6 5 0 r/w 4 pcr6 4 0 r/w 3 pcr6 3 0 r/w 0 pcr6 0 0 r/w 2 pcr6 2 0 r/w 1 pcr6 1 0 r/w bit initial value read/write 7 p6 7 0 r/w 6 p6 6 0 r/w 5 p6 5 0 r/w 4 p6 4 0 r/w 3 p6 3 0 r/w 0 p6 0 0 r/w 2 p6 2 0 r/w 1 p6 1 0 r/w 144 8.6.3 pin functions table 8-15 shows the port 6 pin functions. table 8-15 port 6 pin functions pin pin functions and selection method p6 7 /rp 7 to the pin function depends on bit rter n in rter and bit pcrsn in pcrs. p6 0 /rp 0 (n = 7 to 0) rter n 0 1 pcrs n 0 1 0 1 pin function p6 n input pin p6 n output pin rp n output pin output value pdr6 n high pdrs n impedance pdr6n read p6 n pin pdr6 n pdr6 n pdr6 n value 8.6.4 pin states table 8-16 shows the port 6 pin states in each operating mode. table 8-16 port 6 pin states pin reset sleep subsleep standby watch subactive active p6 7 /rp 7 to high- retains retains high- retains functional functional p6 0 /rp 0 impedance previous previous impedance * previous state state state note: * a high-level signal is output when the mos pull-up is in the on state. 145 8.6.5 operation port 6 can be used as a realtime output port or general input/output port, depending on the contents of rter. the realtime output function is selected when an rter bit is set to 1, and the general input/output function is selected when the bit is cleared to 0. these two functions are described next (see figure 8-6). figure 8-6 port 6 functional block diagram internal bus rter write pdr6 write pdr6 read pcr6 write data selector ck rter ck pdr6 ck pcr6 ck pcrs ck pdrs trgv 146 1. realtime output port operation (rter = 1) the realtime output function of a pin is selected when the corresponding rter bit is set to 1. if a trigger signal is input at the trgv pin, the data in pdr6 is transferred to pdrs, and the pcr6 data is transferred to pcrs. if the pcrs data is 1, the pdrs data is output at the p6/rp pin. if the pcrs data is 0, the p6/rp pin is in the high-impedance state. trigger input at the trgv pin can therefore immediately change the output state (1 or 0) of a pin, or switch the pin between the output and high- impedance states. when pdr6 is read, the pdr6 value is read regardless of the pcr6 and pcrs values. 2. general input/output operation (rter = 0) the general input/output function of a pin is selected when the corresponding rter bit is cleared to 0. when data is written in pdr6, the same data is also written in pdrs. similarly, when data is written in pcr6, the same data is written in pcrs. pdr6 and pdrs function as a single register, as do pcr6 and pcrs, so the pin can be used for general input/output in the usual way. if the pcr6 value is 1, the pdr6 data is output at the p6/rp pin. if the pcr6 value is 0, the p6/rp pin becomes an input pin. when pdr6 is read, if the pcr6 bit is 1 the pdr6 value is read. if the pcr6 bit is 0, the pin value is read. 147 8.7 port 7 8.7.1 overview port 7 is an 8-bit i/o port, configured as shown in figure 8-7. figure 8-7 port 7 pin configuration 8.7.2 register configuration and description table 8-17 shows the port 7 register configuration. table 8-17 port 7 registers name abbrev. r/w initial value address port data register 7 pdr7 r/w h'00 h'ffda port control register 7 pcr7 w h'00 h'ffea p7 7 p7 6 /tmov p7 5 /tmciv p7 4 /tmriv p7 3 p7 2 p7 1 p7 0 port 7 148 1. port data register 7 (pdr7) pdr7 is an 8-bit register that stores data for port 7 pins p7 7 to p7 0 . if port 7 is read while pcr7 bits are set to 1, the values stored in pdr7 are read, regardless of the actual pin states. if port 7 is read while pcr7 bits are cleared to 0, the pin states are read. upon reset, pdr7 is initialized to h'00. 2. port control register 7 (pcr7) pcr7 is an 8-bit register for controlling whether each of the port 7 pins p7 7 to p7 0 functions as an input pin or output pin. setting a pcr7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. upon reset, pcr7 is initialized to h'00. pcr7 is a write-only register, which always reads as all 1s. h037 '92 h8/3834 u.m. pcr7 bit initial value read/write 7 pcr7 0 w 6 pcr7 0 w 5 pcr7 0 w 4 pcr7 0 w 3 pcr7 0 w 0 pcr7 0 w 2 pcr7 0 w 1 pcr7 0 w 7 6 5 4 3 2 1 0 h037 '92 h8/3834 u.m. pdr7 bit initial value read/write 7 p7 0 r/w 6 p7 0 r/w 5 p7 0 r/w 4 p7 0 r/w 3 p7 0 r/w 0 p7 0 r/w 2 p7 0 r/w 1 p7 0 r/w 7 6 5 4 3 2 1 0 149 8.7.3 pin functions table 8-18 shows the port 7 pin functions. table 8-18 port 7 pin functions pin pin functions and selection method p7 7 , p7 3 to p7 0 the pin function depends on bit pcr7 n in pcr7. (n = 7, 3 to 0) pcr7 n 0 1 pin function p7 n input pin p7 n output pin p7 6 /tmov the pin function depends on bit pcr7 6 in pcr7 and bits os3 to os0 in tcsrv. os3 to os0 0000 not 0000 pcr7 6 0 1 * pin function p7 6 input pin p7 6 output pin tmov output pin p7 5 /tmciv the pin function depends on bit pcr7 5 in pcr7. pcr7 5 0 1 pin function p7 5 input pin p7 5 output pin tmciv input pin p7 4 /tmriv the pin function depends on bit pcr7 4 in pcr7. pcr7 4 0 1 pin function p7 4 input pin p7 4 output pin tmriv input pin note: * don? care 8.7.4 pin states table 8-19 shows the port 7 pin states in each operating mode. table 8-19 port 7 pin states pins reset sleep subsleep standby watch subactive active p7 7 to p7 0 high- retains retains high- retains functional functional impedance previous previous impedance previous state state state 150 8.8 port 8 8.8.1 overview port 8 is an 8-bit i/o port configured as shown in figure 8-8. figure 8-8 port 8 pin configuration 8.8.2 register configuration and description table 8-20 shows the port 8 register configuration. table 8-20 port 8 registers name abbrev. r/w initial value address port data register 8 pdr8 r/w h'00 h'ffdb port control register 8 pcr8 w h'00 h'ffeb p8 7 p8 6 /ftid p8 5 /ftic p8 4 /ftib p8 3 //ftia p8 2 /ftob p8 1 /ftoa p8 0 /ftci port 8 151 1. port data register 8 (pdr8) pdr8 is an 8-bit register that stores data for port 8 pins p8 7 to p8 0 . if port 8 is read while pcr8 bits are set to 1, the values stored in pdr8 are read, regardless of the actual pin states. if port 8 is read while pcr8 bits are cleared to 0, the pin states are read. upon reset, pdr8 is initialized to h'00. 2. port control register 8 (pcr8) pcr8 is an 8-bit register for controlling whether each of the port 8 pins p8 7 to p8 0 functions as an input or output pin. setting a pcr8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. upon reset, pcr8 is initialized to h'00. pcr8 is a write-only register, which is always read as all 1s. h037 '92 h8/3834 u.m. pcr8 bit initial value read/write 7 pcr8 0 w 6 pcr8 0 w 5 pcr8 0 w 4 pcr8 0 w 3 pcr8 0 w 0 pcr8 0 w 2 pcr8 0 w 1 pcr8 0 w 7 6 5 4 3 2 1 0 h037 '92 h8/3834 u.m. pdr8 bit initial value read/write 7 p8 0 r/w 6 p8 0 r/w 5 p8 0 r/w 4 p8 0 r/w 3 p8 0 r/w 0 p8 0 r/w 2 p8 0 r/w 1 p8 0 r/w 7 6 5 4 3 2 1 0 152 8.8.3 pin functions table 8-21 shows the port 8 pin functions. table 8-21 port 8 pin functions pin pin functions and selection method p8 7 the pin function depends on bit pcr8 7 in pcr8. pcr8 7 0 1 pin function p8 7 input pin p8 7 output pin p8 6 /ftid the pin function depends on bit pcr8 6 in pcr8. pcr8 6 0 1 pin function p8 6 input pin p8 6 output pin ftid input pin p8 5 /ftic the pin function depends on bit pcr8 5 in pcr8. pcr8 5 0 1 pin function p8 5 input pin p8 5 output pin ftic input pin p8 4 /ftib the pin function depends on bit pcr8 4 in pcr8. p8 4 0 1 pin function p8 4 input pin p8 4 output pin ftib input pin p8 3 /ftia the pin function depends on bit pcr8 3 in pcr8. pcr83 0 1 pin function p8 3 input pin p8 3 output pin ftia input pin p8 2 /ftob the pin function depends on bit pcr8 2 in pcr8 and bit oeb in tocr. oeb 0 1 pcr8 2 0 1 * pin function p8 2 input pin p8 2 output pin ftob output pin note: * don? care 153 table 8-21 port 8 pin functions pin pin functions and selection method p8 1 /ftoa the pin function depends on bit pcr8 1 in pcr8 and bit oea in tocr. oea 0 1 pcr8 1 0 1 * pin function p8 1 input pin p8 1 output pin ftoa output pin p8 0 /ftci the pin function depends on bit pcr8 0 in pcr8. pcr8 0 0 1 pin function p8 0 input pin p8 0 output pin ftci input pin note: * don? care 8.8.4 pin states table 8-22 shows the port 8 pin states in each operating mode. table 8-22 port 8 pin states pins reset sleep subsleep standby watch subactive active p8 7 to p8 0 /ftci high- retains retains high- retains functional functional impedance previous previous impedance previous state state state 154 8.9 port b 8.9.1 overview port b is an 8-bit input-only port, configured as shown in figure 8-9. figure 8-9 port b pin configuration 8.9.2 register configuration and description table 8-23 shows the port b register configuration. table 8-23 port b register name abbrev. r/w address port data register b pdrb r h'ffdd port data register b (pdrb) reading pdrb always gives the pin states. however, if a port b pin is selected as an analog input channel for the a/d converter by amr bits ch3 to ch0, that pin reads 0 regardless of the input voltage. h037 '92 h8/3834 u.m. pdrb bit read/write 7 pb r 6 pb r 5 pb r 4 pb r 3 pb r 0 pb r 2 pb r 1 pb r 3 2 1 0 7 6 5 4 h8/3834 '92 fig. 8-11 pb /an pb /an pb /an pb /an pb /an pb /an pb /an pb /an 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 port b 155 8.9.3 pin functions table 8-24 shows the port b pin functions. table 8-24 port b pin functions pin pin functions and selection method pb n /an n always as below. (n = 7 to 0) pin function pb n input pin or an n input pin 8.9.4 pin states table 8-25 shows the port b pin states in each operating mode. table 8-25 port b pin states pin reset sleep subsleep standby watch subactive active pb n /an n high- high- high- high- high- high- high- impedance impedance impedance impedance impedance impedance impedance (n = 7 to 0) 156 8.10 port c 8.10.1 overview port c is a 4-bit input-only port, configured as shown in figure 8-10. figure 8-10 port c pin configuration 8.10.2 register configuration and description table 8-26 shows the port c register configuration. table 8-26 port c register name abbrev. r/w address port data register c pdrc r h'ffde port data register c (pdrc) reading pdrc always gives the pin states. however, if a port c pin is selected as an analog output channel for the d/a converter by dacr0 bit dae0 and bits daoe3 to daoe0, that pin reads 0 regardless of the output voltage. bits 7 to 4 are always read as 1. h037 '92 h8/3834 u.m. pdrc bit read/write 7 6 5 4 3 pc r 0 pc r 2 pc r 1 pc r 3 2 1 0 pc 3 /da 3 pc 2 /da 2 pc 1 /da 1 pc 0 /da 0 port c 157 8.10.3 pin functions table 8-27 shows the port c pin functions. table 8-27 port c pin functions pin pin functions and selection method pc n /da n always as below. (n = 3 to 0) pin function pc n input pin or da n output pin 8.10.4 pin states table 8-28 shows the port c pin states in each operating mode. table 8-28 port c pin states pin reset sleep subsleep standby watch subactive active pc 3 /da 3 to high- retains retains high- retains functional functional pc 0 /da 0 impedance previous previous impedance previous state state state 158 section 9 timers 9.1 overview the h8/3927 series provides 10 timers: timers a, b1, b2, b3, c, e, v, x, y, and a watchdog timer. the functions of these timers are outlined in table 9-1. table 9-1 timer functions event waveform name functions internal clock input pin output pin remarks timer a 8-bit interval timer ?8 to ?8192 (8 choices) time base w /128 (choice of 4 overflow periods) clock output ?4 to ?32 p1 0 /tmow w /4 to w /32 (8 choices) timer b1 8-bit reload timer ?4 to ?8192 p5 6 /int 6 / ? interval timer (7 choices) tmib event counter timer b2 8-bit reload timer ?4 to ?2048 timer b2 and interval timer (7 choices) timer b3 are timer b3 8-bit reload timer ?4 to ?2048 functionally interval timer (7 choices) identical timer c 8-bit reload timer ?4 to ?8192 p1 3 /tmic counting interval timer w /4 (7 choices) direction can event counter be controlled choice of up- or by software down-counting or hardware timer e 8-bit reload timer ?8 to ?8192 p1 1 /tmoe square wave interval timer (8 choices) output (50% duty) available timer v 8-bit counter ?4 to ?128 p7 5 /tmciv p7 6 /tmov event counter (6 choices) output control by dual compare match counter clearing option externally triggerable 159 table 9-1 timer functions (cont) event waveform name functions internal clock input pin output pin remarks timer x 16-bit free-running ?2 to ?32 p8 0 /ftci p8 1 /ftoa timer (3 choices) p8 2 /ftob 2 output compare channels 4 input capture channels counter clearing option event counter timer y 16-bit reload timer ?4 to ?8192 p5 7 /int 7 / free-running option (7 choices) tmiy event counter watchdog reset signal ?8192 timer generated when 8-bit counter overflows 160 9.2 timer a 9.2.1 overview timer a is an 8-bit timer with interval timing and real-time clock time-base functions. the clock time-base function is available when a 32.768-khz crystal oscillator is connected. a clock signal divided from 32.768 khz or from the system clock can be output at the tmow pin. 1. features features of timer a are given below. choice of eight internal clock sources (?8192, ?4096, ?2048, ?512, ?256, ?128, ?32, ?8). choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer a is used as a clock time base (using a 32.768 khz crystal oscillator). an interrupt is requested when the counter overflows. any of eight clock signals can be output from pin tmow: 32.768 khz divided by 32, 16, 8, or 4 (1 khz, 2 khz, 4 khz, 8 khz), or the system clock divided by 32, 16, 8, or 4. 161 2. block diagram figure 9-2-1 shows a block diagram of timer a. figure 9-2-1 block diagram of timer a 3. pin configuration table 9-2-1 shows the timer a pin configuration. table 9-2-1 pin configuration name abbrev. i/o function clock output tmow output output of waveform generated by timer a output circuit psw internal data bus pss notation: tmow 1/4 tma tca ? /32 ? /16 ? /8 ? /4 w w w w ?32 ?16 ?8 ?4 ? /128 w ?8192, ?4096, ?2048, ?512, ?256, ?128, ?32, ?8 irrta 8 * 64 * 128 * 256 * ? /4 w tma: tca: irrta: psw: pss: note: * can be selected only when the prescaler w output ( w /128) is used as the tca input clock. timer mode register a timer counter a timer a overflow interrupt request flag (interrupt request register 1) prescaler w prescaler s w 162 4. register configuration table 9-2-2 shows the register configuration of timer a. table 9-2-2 timer a registers name abbrev. r/w initial value address timer mode register a tma r/w h'10 h'ffb0 timer counter a tca r h'00 h'ffb1 9.2.2 register descriptions 1. timer mode register a (tma) tma is an 8-bit read/write register for selecting the prescaler, input clock, and output clock. upon reset, tma is initialized to h'10. bits 7 to 5: clock output select (tma7 to tma5) bits 7 to 5 choose which of eight clock signals is output at the tmow pin. the system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. a 32.768 khz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. bit 7 bit 6 bit 5 tma7 tma6 tma5 clock output 0 0 0 ?32 (initial value) 1 ?16 1 0 ?8 1 ?4 1 0 0 w /32 1 w /16 1 0 w /8 1 w /4 h037 '92 h8/3834 u.m. fig. (tma) bit initial value read/write 7 tma7 0 r/w 6 tma6 0 r/w 5 tma5 0 r/w 4 1 3 tma3 0 r/w 0 tma0 0 r/w 2 tma2 0 r/w 1 tma1 0 r/w 163 bit 4: reserved bit bit 4 is reserved; it is always read as 1, and cannot be modified. bits 3 to 0: internal clock select (tma3 to tma0) bits 3 to 0 select the clock input to tca. the selection is made as follows. description bit 3 bit 2 bit 1 bit 0 prescaler and divider ratio tma3 tma2 tma1 tma0 or overflow period function 0 0 0 0 pss, ?8192 (initial value) interval timer 1 pss, ?4096 1 0 pss, ?2048 1 pss, ?512 1 0 0 pss, ?256 1 pss, ?128 1 0 pss, ?32 1 pss, ?8 1 0 0 0 psw, 1 s clock time 1 psw, 0.5 s base 1 0 psw, 0.25 s 1 psw, 0.03125 s 1 0 0 psw and tca are reset 1 1 0 1 164 2. timer counter a (tca) tca is an 8-bit read-only up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tma3 to tma0 in timer mode register a (tma). tca values can be read by the cpu in active mode, but cannot be read in subactive mode. when tca overflows, the irrta bit in interrupt request register 1 (irr1) is set to 1. tca is cleared by setting bits tma3 and tma2 of tma to 11. upon reset, tca is initialized to h'00. 9.2.3 timer operation 1. interval timer operation when bit tma3 in timer mode register a (tma) is cleared to 0, timer a functions as an 8-bit interval timer. upon reset, tca is cleared to h'00 and bit tma3 is cleared to 0, so up-counting and interval timing resume immediately. the clock input to timer a is selected by bits tma2 to tma0 in tma; any of eight internal clock signals output by prescaler s can be selected. after the count value in tca reaches h'ff, the next clock signal input causes timer a to overflow, setting bit irrta to 1 in interrupt request register 1 (irr1). if ienta = 1 in interrupt enable register 1 (ienr1), a cpu interrupt is requested.* at overflow, tca returns to h'00 and starts counting up again. in this mode timer a functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. note: * for details on interrupts, see 3.3, interrupts. h037 '92 h8/3834 u.m. fig. (tca) bit initial value read/write 7 tca7 0 r 6 tca6 0 r 5 tca5 0 r 4 tca4 0 r 3 tca3 0 r 0 tca0 0 r 2 tca2 0 r 1 tca1 0 r 165 2. real-time clock time base operation when bit tma3 in tma is set to 1, timer a functions as a real-time clock time base by counting clock signals output by prescaler w. the overflow period of timer a is set by bits tma1 and tma0 in tma. a choice of four periods is available. in time base operation (tma3 = 1), setting bit tma2 to 1 clears both tca and prescaler w to their initial values of h'00. 3. clock output setting bit tmow in port mode register 1 (pmr1) to 1 causes a clock signal to be output at pin tmow. eight different clock output signals can be selected by means of bits tma7 to tma5 in tma. the system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. a 32.768 khz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, watch mode, subactive mode, and subsleep mode. 9.2.4 timer a operation states table 9-2-3 summarizes the timer a operation states. table 9-2-3 timer a operation states sub- sub- operation mode reset active sleep watch active sleep standby tca interval reset functions functions halted halted halted halted clock time base reset functions functions functions functions functions halted tma reset functions retained retained functions retained retained note: when the real-time clock time base function is selected as the internal clock of tca in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. this may result in a maximum error of 1/?(s) in the count cycle. 166 9.3 timer b1 9.3.1 overview timer b1 is an 8-bit timer that increments each time a clock pulse is input. this timer has two operation modes, interval and auto reload. 1. features features of timer b1 are given below. choice of seven internal clock sources (?8192, ?2048, ?512, ?256, ?64, ?16, ?4) or an external clock (can be used to count external events). an interrupt is requested when the counter overflows. 2. block diagram figure 9-3-1 shows a block diagram of timer b1. figure 9-3-1 block diagram of timer b1 pss tmb1 tcb1 tlb1 tmib notation: irrtb1 tmb1: tcb1: tlb1: irrtb1: pss: timer mode register b1 timer counter b1 timer load register b1 timer b1 interrupt request flag prescaler s internal data bus 167 3. pin configuration table 9-3-1 shows the timer b1 pin configuration. table 9-3-1 pin configuration name abbrev. i/o function timer b1 event input tmib input event input to tcb1 4. register configuration table 9-3-2 shows the register configuration of timer b1. table 9-3-2 timer b1 registers name abbrev. r/w initial value address timer mode register b1 tmb1 r/w h'78 h'ffb2 timer counter b1 tcb1 r h'00 h'ffb3 timer load register b1 tlb1 w h'00 h'ffb3 9.3.2 register descriptions 1. timer mode register b1 (tmb1) tmb1 is an 8-bit read/write register for selecting the auto-reload function and input clock. upon reset, tmb1 is initialized to h'78. bit 7: auto-reload function select (tmb17) bit 7 selects whether timer b1 is used as an interval timer or auto-reload timer. bit 7 tmb17 description 0 interval timer function selected (initial value) 1 auto-reload function selected bit initial value read/write 7 tmb17 0 r/w 6 ? 1 5 ? 1 4 ? 1 3 ? 1 0 tmb10 0 r/w 2 tmb12 0 r/w 1 tmb11 0 r/w 168 bits 6 to 3: reserved bits bits 6 to 3 are reserved; they are always read as 1, and cannot be modified. bits 2 to 0: clock select (tmb12 to tmb10) bits 2 to 0 select the clock input to tcb1. for external event counting, either the rising or falling edge can be selected. bit 2 bit 1 bit 0 tmb12 tmb11 tmb10 description 0 0 0 internal clock: ?8192 (initial value) 0 0 1 internal clock: ?2048 0 1 0 internal clock: ?512 0 1 1 internal clock: ?256 1 0 0 internal clock: ?64 1 0 1 internal clock: ?16 1 1 0 internal clock: ?4 1 1 1 external event (tmib): rising or falling edge * note: * the edge of the external event signal is selected by bit integ6 in interrupt edge select register 2 (iegr2). see 3.3.2, interrupt control registers, for details. 2. timer counter b1 (tcb1) tcb1 is an 8-bit read-only up-counter, which is incremented by internal clock or external event input. the clock source for input to this counter is selected by bits tmb12 to tmb10 in timer mode register b1 (tmb1). tcb1 values can be read by the cpu at any time. when tcb1 overflows from h'ff to h'00 or to the value set in tlb1, the irrtb1 bit in irr1 is set to 1. tcb1 is allocated to the same address as tlb1. upon reset, tcb1 is initialized to h'00. bit initial value read/write 7 tcb17 0 r 6 tcb16 0 r 5 tcb15 0 r 4 tcb14 0 r 3 tcb13 0 r 0 tcb10 0 r 2 tcb12 0 r 1 tcb11 0 r 169 3. timer load register b1 (tlb1) tlb1 is an 8-bit write-only register for setting the reload value of timer counter b1. when a reload value is set in tlb1, the same value is loaded into timer counter b1 (tcb1) as well, and tcb1 starts counting up from that value. when tcb1 overflows during operation in auto- reload mode, the tlb1 value is loaded into tcb1. accordingly, overflow periods can be set within the range of 1 to 256 input clocks. the same address is allocated to tlb1 as to tcb1. upon reset, tlb1 is initialized to h'00. 9.3.3 timer operation 1. interval timer operation when bit tmb17 in timer mode register b1 (tmb1) is cleared to 0, timer b1 functions as an 8-bit interval timer. upon reset, tcb1 is cleared to h'00 and bit tmb17 is cleared to 0, so up-counting and interval timing resume immediately. the clock input to timer b1 is selected from seven internal clock signals output by prescaler s, or an external clock input at pin tmib. the selection is made by bits tmb12 to tmb10 of tmb1. after the count value in tcb1 reaches h'ff, the next clock signal input causes timer b1 to overflow, setting bit irrtb1 to 1 in interrupt request register 1 (irr1). if ientb1 = 1 in interrupt enable register 1 (ienr1), a cpu interrupt is requested.* at overflow, tcb1 returns to h'00 and starts counting up again. during interval timer operation (tmb17 = 0), when a value is set in timer load register b1 (tlb1), the same value is set in tcb1. note: * for details on interrupts, see 3.3, interrupts. bit initial value read/write 7 tlb17 0 w 6 tlb16 0 w 5 tlb15 0 w 4 tlb14 0 w 3 tlb13 0 w 0 tlb10 0 w 2 tlb12 0 w 1 tlb11 0 w 170 2. auto-reload timer operation setting bit tmb17 in tmb1 to 1 causes timer b1 to function as an 8-bit auto-reload timer. when a reload value is set in tlb1, the same value is loaded into tcb1, becoming the value from which tcb1 starts its count. after the count value in tcb1 reaches h'ff, the next clock signal input causes timer b1 to overflow. the tlb1 value is then loaded into tcb1, and the count continues from that value. the overflow period can be set within a range from 1 to 256 input clocks, depending on the tlb1 value. the clock sources and interrupts in auto-reload mode are the same as in interval mode. in auto-reload mode (tmb17 = 1), when a new value is set in tlb1, the tlb1 value is also set in tcb1. 3. event counter operation timer b1 can operate as an event counter, counting rising or falling edges of an external event signal input at pin tmib. external event counting is selected by setting bits tmb12 to tmb10 in timer mode register b1 to all 1s (111). when timer b1 is used to count external event input, bit inten6 in ienr3 should be cleared to 0 to disable int 6 interrupt requests. 9.3.4 timer b1 operation states table 9-3-3 summarizes the timer b1 operation states. table 9-3-3 timer b1 operation states sub- sub- operation mode reset active sleep watch active sleep standby tcb1 interval reset functions functions halted halted halted halted auto reload reset functions functions halted halted halted halted tmb1 reset functions retained retained retained retained retained 171 9.4 timer b2 9.4.1 overview timer b2 is an 8-bit timer that increments each time a clock pulse is input. this timer has two operation modes, interval and auto reload. 1. features features of timer b2 are given below. choice of seven internal clock sources (?2048, ?512, ?256, ?64, ?16, ?8, ?4). an interrupt is requested when the counter overflows. 2. block diagram figure 9-4-1 shows a block diagram of timer b2. figure 9-4-1 block diagram of timer b2 pss tmb2 tcb2 tlb2 notation: irrtb2 tmb2: tcb2: tlb2: irrtb2: pss: timer mode register b2 timer counter b2 timer load register b2 timer b2 interrupt request flag prescaler s internal data bus 172 3. register configuration table 9-4-1 shows the register configuration of timer b2. table 9-4-1 timer b2 registers name abbrev. r/w initial value address timer mode register b2 tmb2 r/w h'78 h'ffc2 timer counter b2 tcb2 r h'00 h'ffc3 timer load register b2 tlb2 w h'00 h'ffc3 9.4.2 register descriptions 1. timer mode register b2 (tmb2) tmb2 is an 8-bit read/write register for selecting the auto-reload function and input clock. upon reset, tmb2 is initialized to h'78. bit 7: auto-reload function select (tmb27) bit 7 selects whether timer b2 is used as an interval timer or auto-reload timer. bit 7 tmb27 description 0 interval timer function selected (initial value) 1 auto-reload function selected bits 6 to 3: reserved bits bits 6 to 3 are reserved; they are always read as 1, and cannot be modified. bit initial value read/write 7 tmb27 0 r/w 6 ? 1 5 ? 1 4 ? 1 3 ? 1 0 tmb20 0 r/w 2 tmb22 0 r/w 1 tmb21 0 r/w 173 bits 2 to 0: clock select (tmb22 to tmb20) bits 2 to 0 select the clock input to tcb2. bit 2 bit 1 bit 0 tmb22 tmb21 tmb20 description 0 0 0 internal clock: ?2048 (initial value) 0 0 1 internal clock: ?512 0 1 0 internal clock: ?256 0 1 1 internal clock: ?64 1 0 0 internal clock: ?16 1 0 1 internal clock: ?8 1 1 0 internal clock: ?4 1 1 1 reserved 2. timer counter b2 (tcb2) tcb2 is an 8-bit read-only up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tmb22 to tmb20 in timer mode register b2 (tmb2). tcb2 values can be read by the cpu at any time. when tcb2 overflows from h'ff to h'00 or to the value set in tlb2, the irrtb2 bit in irr2 is set to 1. tcb2 is allocated to the same address as tlb2. upon reset, tcb2 is initialized to h'00. bit initial value read/write 7 tcb27 0 r 6 tcb26 0 r 5 tcb25 0 r 4 tcb24 0 r 3 tcb23 0 r 0 tcb20 0 r 2 tcb22 0 r 1 tcb21 0 r 174 3. timer load register b2 (tlb2) tlb2 is an 8-bit write-only register for setting the reload value of timer counter b2. when a reload value is set in tlb2, the same value is loaded into timer counter b2 (tcb2) as well, and tcb2 starts counting up from that value. when tcb2 overflows during operation in auto- reload mode, the tlb2 value is loaded into tcb2. accordingly, overflow periods can be set within the range of 1 to 256 input clocks. the same address is allocated to tlb2 as to tcb2. upon reset, tlb2 is initialized to h'00. 9.4.3 timer operation 1. interval timer operation when bit tmb27 in timer mode register b2 (tmb2) is cleared to 0, timer b2 functions as an 8-bit interval timer. upon reset, tcb2 is cleared to h'00 and bit tmb27 is cleared to 0, so up-counting and interval timing resume immediately. the clock input to timer b2 is selected from seven internal clock signals output by prescaler s. the selection is made by bits tmb22 to tmb20 of tmb2. after the count value in tcb2 reaches h'ff, the next clock signal input causes timer b2 to overflow, setting bit irrtb2 to 1 in interrupt request register 2 (irr2). if ientb2 = 1 in interrupt enable register 2 (ienr2), a cpu interrupt is requested.* at overflow, tcb2 returns to h'00 and starts counting up again. during interval timer operation (tmb27 = 0), when a value is set in timer load register b2 (tlb2), the same value is set in tcb2. note: * for details on interrupts, see 3.3, interrupts. bit initial value read/write 7 tlb27 0 w 6 tlb26 0 w 5 tlb25 0 w 4 tlb24 0 w 3 tlb23 0 w 0 tlb20 0 w 2 tlb22 0 w 1 tlb21 0 w 175 2. auto-reload timer operation setting bit tmb27 in tmb2 to 1 causes timer b2 to function as an 8-bit auto-reload timer. when a reload value is set in tlb2, the same value is loaded into tcb2, becoming the value from which tcb2 starts its count. after the count value in tcb2 reaches h'ff, the next clock signal input causes timer b2 to overflow. the tlb2 value is then loaded into tcb2, and the count continues from that value. the overflow period can be set within a range from 1 to 256 input clocks, depending on the tlb2 value. the clock sources and interrupts in auto-reload mode are the same as in interval mode. in auto-reload mode (tmb27 = 1), when a new value is set in tlb2, the tlb2 value is also set in tcb2. 9.4.4 timer b2 operation states table 9-4-2 summarizes the timer b2 operation states. table 9-4-2 timer b2 operation states sub- sub- operation mode reset active sleep watch active sleep standby tcb2 interval reset functions functions halted halted halted halted auto reload reset functions functions halted halted halted halted tmb2 reset functions retained retained retained retained retained 176 9.5 timer b3 9.5.1 overview timer b3 is an 8-bit timer that increments each time a clock pulse is input. this timer has two operation modes, interval and auto reload. 1. features features of timer b3 are given below. choice of seven internal clock sources (?2048, ?512, ?256, ?64, ?16, ?8, ?4). an interrupt is requested when the counter overflows. 2. block diagram figure 9-5-1 shows a block diagram of timer b3. figure 9-5-1 block diagram of timer b3 pss tmb3 tcb3 tlb3 notation: irrtb3 tmb3: tcb3: tlb3: irrtb3: pss: timer mode register b3 timer counter b3 timer load register b3 timer b3 interrupt request flag prescaler s internal data bus 177 3. register configuration table 9-5-1 shows the register configuration of timer b3. table 9-5-1 timer b3 registers name abbrev. r/w initial value address timer mode register b3 tmb3 r/w h'78 h'ffe2 timer counter b3 tcb3 r h'00 h'ffe3 timer load register b3 tlb3 w h'00 h'ffe3 9.5.2 register descriptions 1. timer mode register b3 (tmb3) tmb3 is an 8-bit read/write register for selecting the auto-reload function and input clock. upon reset, tmb3 is initialized to h'78. bit 7: auto-reload function select (tmb37) bit 7 selects whether timer b3 is used as an interval timer or auto-reload timer. bit 7 tmb37 description 0 interval timer function selected (initial value) 1 auto-reload function selected bits 6 to 3: reserved bits bits 6 to 3 are reserved; they are always read as 1, and cannot be modified. bit initial value read/write 7 tmb37 0 r/w 6 ? 1 5 ? 1 4 ? 1 3 ? 1 0 tmb30 0 r/w 2 tmb32 0 r/w 1 tmb31 0 r/w 178 bits 2 to 0: clock select (tmb32 to tmb30) bits 2 to 0 select the clock input to tcb3. bit 2 bit 1 bit 0 tmb32 tmb31 tmb30 description 0 0 0 internal clock: ?2048 (initial value) 0 0 1 internal clock: ?512 0 1 0 internal clock: ?256 0 1 1 internal clock: ?64 1 0 0 internal clock: ?16 1 0 1 internal clock: ?8 1 1 0 internal clock: ?4 1 1 1 reserved 2. timer counter b3 (tcb3) tcb3 is an 8-bit read-only up-counter, which is incremented by internal clock or external event input. the clock source for input to this counter is selected by bits tmb32 to tmb30 in timer mode register b3 (tmb3). tcb3 values can be read by the cpu at any time. when tcb3 overflows from h'ff to h'00 or to the value set in tlb3, the irrtb3 bit in irr2 is set to 1. tcb3 is allocated to the same address as tlb3. upon reset, tcb3 is initialized to h'00. bit initial value read/write 7 tcb37 0 r 6 tcb36 0 r 5 tcb35 0 r 4 tcb34 0 r 3 tcb33 0 r 0 tcb30 0 r 2 tcb32 0 r 1 tcb31 0 r 179 3. timer load register b3 (tlb3) tlb3 is an 8-bit write-only register for setting the reload value of timer counter b3. when a reload value is set in tlb3, the same value is loaded into timer counter b3 (tcb3) as well, and tcb3 starts counting up from that value. when tcb3 overflows during operation in auto- reload mode, the tlb3 value is loaded into tcb3. accordingly, overflow periods can be set within the range of 1 to 256 input clocks. the same address is allocated to tlb3 as to tcb3. upon reset, tlb3 is initialized to h'00. 9.5.3 timer operation 1. interval timer operation when bit tmb37 in timer mode register b3 (tmb3) is cleared to 0, timer b3 functions as an 8-bit interval timer. upon reset, tcb3 is cleared to h'00 and bit tmb37 is cleared to 0, so up-counting and interval timing resume immediately. the clock input to timer b3 is selected from eight internal clock signals output by prescaler s. the selection is made by bits tmb32 to tmb30 of tmb3. after the count value in tcb3 reaches h'ff, the next clock signal input causes timer b3 to overflow, setting bit irrtb3 to 1 in interrupt request register 2 (irr2). if ientb3 = 1 in interrupt enable register 2 (ienr2), a cpu interrupt is requested.* at overflow, tcb3 returns to h'00 and starts counting up again. during interval timer operation (tmb37 = 0), when a value is set in timer load register b3 (tlb3), the same value is set in tcb3. note: * for details on interrupts, see 3.3, interrupts. bit initial value read/write 7 tlb37 0 w 6 tlb36 0 w 5 tlb35 0 w 4 tlb34 0 w 3 tlb33 0 w 0 tlb30 0 w 2 tlb32 0 w 1 tlb31 0 w 180 2. auto-reload timer operation setting bit tmb37 in tmb3 to 1 causes timer b3 to function as an 8-bit auto-reload timer. when a reload value is set in tlb3, the same value is loaded into tcb3, becoming the value from which tcb3 starts its count. after the count value in tcb3 reaches h'ff, the next clock signal input causes timer b3 to overflow. the tlb3 value is then loaded into tcb3, and the count continues from that value. the overflow period can be set within a range from 1 to 256 input clocks, depending on the tlb3 value. the clock sources and interrupts in auto-reload mode are the same as in interval mode. in auto-reload mode (tmb37 = 1), when a new value is set in tlb3, the tlb3 value is also set in tcb3. 9.5.4 timer b3 operation states table 9-5-2 summarizes the timer b3 operation states. table 9-5-2 timer b3 operation states sub- sub- operation mode reset active sleep watch active sleep standby tcb3 interval reset functions functions halted halted halted halted auto reload reset functions functions halted halted halted halted tmb3 reset functions retained retained retained retained retained 181 9.6 timer c 9.6.1 overview timer c is an 8-bit timer that increments or decrements each time a clock pulse is input. this timer has two operation modes, interval and auto reload. 1. features the main features of timer c are given below. choice of seven internal clock sources (?8192, ?2048, ?512, ?64, ?16, ?4, w /4) or an external clock (can be used to count external events). an interrupt is requested when the counter overflows. can be switched between up- and down-counting by software or hardware. when w /4 is selected as the internal clock source, or when an external clock is selected, timer c can function in subactive mode and subsleep mode. 2. block diagram figure 9-6-1 shows a block diagram of timer c. figure 9-6-1 block diagram of timer c tmc tlc notation: irrtc tmc: tcc: tlc: irrtc: pss: timer mode register c timer counter c timer load register c timer c overflow interrupt request flag prescaler s internal data bus ud pss tmic w /4 tcc 182 3. pin configuration table 9-6-1 shows the timer c pin configuration. table 9-6-1 pin configuration name abbrev. i/o function timer c event input tmic input event input to tcc timer c up/down control ud input selection of counting direction 4. register configuration table 9-6-2 shows the register configuration of timer c. table 9-6-2 timer c registers name abbrev. r/w initial value address timer mode register c tmc r/w h'18 h'ffb4 timer counter c tcc r h'00 h'ffb5 timer load register c tlc w h'00 h'ffb5 9.6.2 register descriptions 1. timer mode register c (tmc) tmc is an 8-bit read/write register for selecting the auto-reload function, counting direction, and input clock. upon reset, tmc is initialized to h'18. h037 '92 h8/3834 u.m. fig. (tmc) bit initial value read/write 7 tmc7 0 r/w 6 tmc6 0 r/w 5 tmc5 0 r/w 4 1 3 1 0 tmc0 0 r/w 2 tmc2 0 r/w 1 tmc1 0 r/w 183 bit 7: auto-reload function select (tmc7) bit 7 selects whether timer c is used as an interval timer or auto-reload timer. bit 7 tmc7 description 0 interval timer function selected (initial value) 1 auto-reload function selected bits 6 and 5: counter up/down control (tmc6 and tmc5) these bits select the counting direction of timer counter c (tcc), or allow hardware to control the counting direction using pin ud. bit 6 bit 5 tmc6 tmc5 description 0 0 tcc is an up-counter (initial value) 0 1 tcc is a down-counter 1 * tcc up/down control is determined by input at pin ud. tcc is a down- counter if the ud input is high, and an up-counter if the ud input is low note: * don? care bits 4 and 3: reserved bits bits 4 and 3 are reserved; they are always read as 1, and cannot be modified. bits 2 to 0: clock select (tmc2 to tmc0) bits 2 to 0 select the clock input to tcc. for external clock counting, either the rising or falling edge can be selected. bit 2 bit 1 bit 0 tmc2 tmc1 tmc0 description 0 0 0 internal clock: ?8192 (initial value) 0 0 1 internal clock: ?2048 0 1 0 internal clock: ?512 0 1 1 internal clock: ?64 1 0 0 internal clock: ?16 1 0 1 internal clock: ?4 1 1 0 internal clock: w /4 1 1 1 external event (tmic): rising or falling edge * note: * the edge of the external event signal is selected by bit tciceg in port mode register 1 (pmr1). for details, see 8.2.2 (4), port mode register 1 (pmr1). 184 2. timer counter c (tcc) tcc is an 8-bit read-only up-/down-counter, which is incremented or decremented by internal clock or external event input. the clock source for input to this counter is selected by bits tmc2 to tmc0 in timer mode register c (tmc). tcc values can be read by the cpu at any time. when tcc overflows (from h'ff to h'00 or to the value set in tlc) or underflows (from h'00 to h'ff or to the value set in tlc), the irrtc bit in interrupt request register 2 (irr2) is set to 1. tcc is allocated to the same address as timer load register c (tlc). upon reset, tcc is initialized to h'00. 3. timer load register c (tlc) tlc is an 8-bit write-only register for setting the reload value of tcc. when a reload value is set in tlc, the same value is loaded into timer counter c (tcc) as well, and tcc starts counting up or down from that value. when tcc overflows or underflows during operation in auto-reload mode, the tlc value is loaded into tcc. accordingly, overflow and underflow periods can be set within the range of 1 to 256 input clocks. the same address is allocated to tlc as to tcc. upon reset, tlc is initialized to h'00. h037 '92 h8/3834 u.m. fig. (tlc) bit initial value read/write 7 tlc7 0 w 6 tlc6 0 w 5 tlc5 0 w 4 tlc4 0 w 3 tlc3 0 w 0 tlc0 0 w 2 tlc2 0 w 1 tlc1 0 w h037 '92 h8/3834 u.m. fig. (tcc) bit initial value read/write 7 tcc7 0 r 6 tcc6 0 r 5 tcc5 0 r 4 tcc4 0 r 3 tcc3 0 r 0 tcc0 0 r 2 tcc2 0 r 1 tcc1 0 r 185 9.6.3 timer operation 1. interval timer operation when bit tmc7 in timer mode register c (tmc) is cleared to 0, timer c functions as an 8-bit interval timer. upon reset, timer counter c (tcc) is initialized to h'00 and tmc to h'18, so counting and interval timing resume immediately. the clock input to timer c is selected from seven internal clock signals output by prescalers s and w, or an external clock input at pin tmic. the selection is made by bits tmc2 to tmc0 in tmc. either software or hardware can control whether tcc counts up or down. the selection is made by tmc bits tmc6 and tmc5. after the count value in tcc reaches h'ff (h'00), the next clock signal input causes timer c to overflow (underflow), setting bit irrtc to 1 in interrupt request register 2 (irr2). if ientc = 1 in interrupt enable register 2 (ienr2), a cpu interrupt is requested.* at overflow or underflow, tcc returns to h'00 or h'ff and starts counting up or down again. during interval timer operation (tmc7 = 0), when a value is set in timer load register c (tlc), the same value is set in tcc. note: * for details on interrupts, see 3.3, interrupts. 2. auto-reload timer operation setting bit tmc7 in tmc to 1 causes timer c to function as an 8-bit auto-reload timer. when a reload value is set in tlc, the same value is loaded into tcc, becoming the value from which tcc starts its count. after the count value in tcc reaches h'ff (h'00), the next clock signal input causes timer c to overflow (underflow). the tlc value is then loaded into tcc, and the count continues from that value. the overflow (underflow) period can be set within a range from 1 to 256 input clocks, depending on the tlc value. the clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval mode. in auto-reload mode (tmc7 = 1), when a new value is set in tlc, the tlc value is also set in tcc. 186 3. event counter operation timer c can operate as an event counter, counting an event signal input at pin tmic. external event counting is selected by setting tmc bits tmc2 to tmc0 to all 1s (111). tcc counts up or down at the rising or falling edge of the input at pin tmic. 4. tcc up/down control by hardware the counting direction of timer c can be controlled by input at pin ud. when bit tmc6 in tmc is set to 1, high-level input at the ud pin selects down-counting, while low-level input selects up- counting. when using input at pin ud for this control function, set the ud bit in port mode register 2 (pmr2) to 1. 9.6.4 timer c operation states table 9-6-3 summarizes the timer c operation states. table 9-6-3 timer c operation states sub- sub- operation mode reset active sleep watch active sleep standby tcc interval reset functions functions halted functions/ functions/ halted halted * halted * tcc auto reload reset functions functions halted functions/ functions/ halted halted * halted * tmc reset functions retained retained functions retained retained note: when w /4 is selected as the internal clock of tcc in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. this may result in a maximum error of 1/?(s) in the count cycle. * when timer c is operated in subactive mode or subsleep mode, either an external clock or the w /4 internal clock must be selected. the counter will not operate in these modes if another clock is selected. if the internal w /4 clock is selected when w /8 is being used as the subclock sub , the lower 2 bits of the counter will operate on the same cycle, with the least significant bit not being counted. 187 9.7 timer e 9.7.1 overview timer e is an 8-bit timer that increments each time a clock pulse is input. this timer has two operation modes, interval and auto reload. it can also output a square wave with a 50% duty cycle, using either its overflow signal or a signal from prescaler s. 1. features features of timer e are given below. choice of eight internal clock sources (?8192, ?4096, ?2048, ?512, ?256, ?128, ?32, ?8). an interrupt is requested when the counter overflows. output of a square wave with 50% duty cycle and fixed frequency, given by the prescaler 1.95 khz or 3.9 khz when ?= 4 mhz 0.98 khz or 1.95 khz when ?= 2 mhz output of a square wave with 50% duty cycle and arbitrary frequency, using the overflow signal 2. block diagram figure 9-7-1 shows a block diagram of timer e. figure 9-7-1 block diagram of timer e pss tle tce notation: irrte tme: tce: tle: irrte: pss: timer mode register e timer counter e timer load register e timer e interrupt request flag prescaler s internal data bus tme tmoe 188 3. pin configuration table 9-7-1 shows the timer e pin configuration. table 9-7-1 pin configuration name abbrev. i/o function timer e output tmoe output timer e waveform output 4. register configuration table 9-7-2 shows the register configuration of timer e. table 9-7-2 timer e registers name abbrev. r/w initial value address timer mode register e tme r/w h'08 h'ffb6 timer counter e tce r h'00 h'ffb7 timer load register e tle w h'00 h'ffb7 9.7.2 register descriptions 1. timer mode register e (tme) tme is an 8-bit read/write register for selecting the auto-reload function and input clock. upon reset, tme is initialized to h'08. bit 7: auto-reload function select (tme7) bit 7 selects whether timer e is used as an interval timer or auto-reload timer. bit 7 tme7 description 0 interval timer function selected (initial value) 1 auto-reload function selected bit initial value read/write 7 tme7 0 r/w 6 tmoeon 0 r/w 5 freq 0 r/w 4 vrfr 0 r/w 3 ? 1 0 tme0 0 r/w 2 tme2 0 r/w 1 tme1 0 r/w 189 bit 6: timer e output on/off (tmoeon) bit 5: fixed frequency select (freq) bit 4: variable frequency select (vrfr) output is controlled by the combination of bits tmoeon, freq, and vrfr. bit 6 bit 5 bit 4 tmoeon freq vrfr description 0 * * low level output (initial value) 1 0 0 fixed-frequency output (?2048) 1.95 khz (?= 4 mhz), 0.98 khz (?= 2 mhz) 1 1 0 fixed-frequency output (?1024) 3.9 khz (?= 4 mhz), 1.95 khz (?= 2 mhz) 1 * 1 variable-frequency output: toggles at timer e overflow note: * don? care bit 3: reserved bit bit 3 is reserved; it is always read as 1, and cannot be modified. bits 2 to 0: clock select (tme2 to tme0) bits 2 to 0 select the clock input to tce. bit 2 bit 1 bit 0 tme2 tme1 tme0 description 0 0 0 internal clock: ?8192 (initial value) 0 0 1 internal clock: ?4096 0 1 0 internal clock: ?2048 0 1 1 internal clock: ?512 1 0 0 internal clock: ?256 1 0 1 internal clock: ?128 1 1 0 internal clock: ?32 1 1 1 internal clock: ?8 190 2. timer counter e (tce) tce is an 8-bit read-only up-counter, which is incremented by internal clock input. the clock source for input to this counter is selected by bits tme2 to tme0 in timer mode register e (tme). tce values can be read by the cpu at any time. when tce overflows from h'ff to h'00 or to the value set in tle, the irrte bit in irr2 is set to 1. tce is allocated to the same address as tle. upon reset, tce is initialized to h'00. 3. timer load register e (tle) tle is an 8-bit write only register for setting the reload value of timer counter e. when a reload value is set in tle, the same value is loaded into timer counter e (tce) as well, and tce starts counting up from that value. when tce overflows during operation in auto-reload mode, the tle value is loaded into tce. accordingly, overflow periods can be set within the range of 1 to 256 input clocks. the same address is allocated to tle as to tce. upon reset, tle is initialized to h'00. bit initial value read/write 7 tle7 0 w 6 tle6 0 w 5 tle5 0 w 4 tle4 0 w 3 tle3 0 w 0 tle0 0 w 2 tle2 0 w 1 tle1 0 w bit initial value read/write 7 tce7 0 r 6 tce6 0 r 5 tce5 0 r 4 tce4 0 r 3 tce3 0 r 0 tce0 0 r 2 tce2 0 r 1 tce1 0 r 191 9.7.3 timer operation 1. interval timer operation when bit tme7 in timer mode register e (tme) is cleared to 0, timer e functions as an 8-bit interval timer. upon reset, tce is cleared to h'00 and bit tme7 is cleared to 0, so up-counting and interval timing resume immediately. the clock input to timer e is selected from eight internal clock signals output by prescaler s. the selection is made by bits tme2 to tme0 of tme. after the count value in tce reaches h'ff, the next clock signal input causes timer e to overflow, setting bit irrte to 1 in interrupt request register 2 (irr2). if iente = 1 in interrupt enable register 2 (ienr2), a cpu interrupt is requested.* at overflow, tce returns to h'00 and starts counting up again. during interval timer operation (tme7 = 0), when a value is set in timer load register e (tle), the same value is set in tce. note: * for details on interrupts, see 3.3, interrupts. 2. auto-reload timer operation setting bit tme7 in tme to 1 causes timer e to function as an 8-bit auto-reload timer. when a reload value is set in tle, the same value is loaded into tce, becoming the value from which tce starts its count. after the count value in tce reaches h'ff, the next clock signal input causes timer e to overflow. the tle value is then loaded into tce, and the count continues from that value. the overflow period can be set within a range from 1 to 256 input clocks, depending on the tle value. the clock sources and interrupts in auto-reload mode are the same as in interval mode. in auto-reload mode (tme7 = 1), when a new value is set in tle, the tle value is also set in tce. 192 3. square-wave output depending on tme settings, a square wave with 50% duty cycle can be output from the tmoe pin. when the vrfr bit is cleared to 0 in tme, the output waveform has a fixed frequency selected by the freq bit. for the output frequencies, see 9.7.2 (1), timer mode register e (tme). when vrfr is set to 1, the output toggles between the high and low levels each time timer e overflows. (see figure 9-7-2.) the output waveform can have any frequency in the ranges shown in table 9-7-3. the frequency is controlled by the overflow period selected by tle when timer e operates in auto-reload mode (tme7 = 1), and by the clock source selected by bits tme2 to tme0. figure 9-7-2 waveform output by timer e overflow timer e value = h'ff tle value (auto-reload mode) tmoe output waveform timer e interrupt request 193 table 9-7-3 frequency of waveforms output by timer e overflow output waveform ( = 2 mhz) 1 count (tle = h'ff) 2 to 256 counts (tle = h'00) 2 output output internal clock count time frequency count time frequency ?8 (250 khz) 8 s 125 khz to 2024 s 488.3 hz ?32 (62.5 khz) 32 s 31.25 khz to 8192 s 122.1 hz ?128 (15.62 khz) 128 s 7.8125 khz to 32.768 ms 30.5 hz ?256 (7.8125 khz) 256 s 3.9063 khz to 65.536 ms 15.3 hz ?512 (3.9062 khz) 512 s 1.9531 khz to 131.072 ms 7.63 hz ?2048 (976.5 hz) 2.048 ms 488.3 hz to 524.288 ms 1.91 hz ?4096 (488.2 hz) 4.096 ms 244.1 hz to 1048.576 ms 0.95 hz ?8192 (244.1 hz) 8.192 ms 122.1 hz to 2097.152 ms 0.477 hz output waveform ( = 4 mhz) 1 count (tle = h'ff) 2 to 256 counts (tle = h'00) 2 output output internal clock count time frequency count time frequency ?8 (500 khz) 4 s 250 khz to 1024 s 976.6 hz ?32 (125 khz) 16 s 62.5 khz to 4096 s 244.1 hz ?128 (31.25 khz) 64 s 15.625 khz to 16.348 ms 61.0 hz ?256 (15.625 khz) 128 s 7.8125 khz to 32.768 ms 30.5 hz ?512 (7.8125 khz) 256 s 3.9063 khz to 65.536 ms 15.3 hz ?2048 (1.963 hz) 1.024 ms 976.6 hz to 262.144 ms 3.8 hz ?4096 (976.52 hz) 2.048 ms 488.3 hz to 524.288 ms 1.91 hz ?8192 (488.2 hz) 4.096 ms 244.1 hz to 1048.576 ms 0.95 hz 9.7.4 timer e operation states table 9-7-4 summarizes the timer e operation states. table 9-7-4 timer e operation states sub- sub- operation mode reset active sleep watch active sleep standby tce interval reset functions functions halted halted halted halted auto reload reset functions functions halted halted halted halted tme reset functions functions retained retained retained retained 194 9.8 timer v 9.8.1 overview timer v is an 8-bit timer based on an 8-bit counter. timer v counts external events. also compare match signals can be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. counting can be initiated by a trigger input at the trgv pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. the trigger input signal is shared with the realtime port. 1. features features of timer v are given below. choice of six internal clock sources (?128, ?64, ?32, ?16, ?8, ?4) or an external clock (can be used as an external event counter). counter can be cleared by compare match a or b, or by an external reset signal. if the trigger function is selected, the counter can be halted when cleared. timer output is controlled by two independent compare match signals, enabling pulse output with an arbitrary duty cycle, pwm output, and other applications. three interrupt sources: two compare match, one overflow counting can be initiated by trigger input at the trgv pin. the rising edge, falling edge, or both edges of the trgv input can be selected. 195 2. block diagram figure 9-8-1 shows a block diagram of timer v. figure 9-8-1 block diagram of timer v trgv tmciv tmriv tmov cmia cmib ovi internal data bus trigger control comparator clock select comparator clear control interrupt request control output control time constant register a time constant register b timer counter v timer control/status register v timer control register v0 timer control register v1 prescaler s compare-match interrupt a compare-match interrupt b overflow interrupt notation: tcora: tcorb: tcntv: tcsrv: tcrv0: tcrv1: pss: cmia: cmib: ovi: pss tcrv1 tcorb tcntv tcora tcrvo tcsrv 196 3. pin configuration table 9-8-1 shows the timer v pin configuration. table 9-8-1 pin configuration name abbrev. i/o function timer v output tmov output timer v waveform output timer v clock input tmciv input clock input to tcntv timer v reset input tmriv input external input to reset tcntv trigger input trgv input trigger input to initiate counting 4. register configuration table 9-8-2 shows the register configuration of timer v. table 9-8-2 timer v registers name abbrev. r/w initial value address timer control register v0 tcrv0 r/w h'00 h'ffb8 timer control/status register v tcsrv r/(w) * h'10 h'ffb9 time constant register a tcora r/w h'ff h'ffba time constant register b tcorb r/w h'ff h'ffbb timer counter v tcntv r/w h'00 h'ffbc timer control register v1 tcrv1 r/w h'e2 h'ffbd note: * bits 7 to 5 can only be written with 0, for flag clearing. 197 9.8.2 register descriptions 1. timer counter v (tcntv) tcntv is an 8-bit read/write up-counter which is incremented by internal or external clock input. the clock source is selected by bits cks2 to cks0 in tcrv0. the tcntv value can be read and written by the cpu at any time. tcntv can be cleared by an external reset signal, or by compare match a or b. the clearing signal is selected by bits cclr1 and cclr0 in tcrv0. when tcntv overflows from h'ff to h'00, ovf is set to 1 in tcsrv. tcntv is initialized to h'00 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. 2. time constant registers a and b (tcora, tcorb) tcora and tcorb are 8-bit read/write registers. tcora and tcntv are compared at all times, except during the t 3 state of a tcora write cycle. when the tcora and tcntv contents match, cmfa is set to 1 in tcsrv. if cmiea is also set to 1 in tcrv0, a cpu interrupt is requested. timer output from the tmov pin can be controlled by a signal resulting from compare match, according to the settings of bits os3 to os0 in tcsrv. tcora is initialized to h'ff upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. tcorb is similar to tcora. bit initial value read/write 7 tcorn 7 1 r/w 6 tcorn 6 1 r/w 5 tcorn 5 1 r/w 4 tcorn 4 1 r/w 3 tcorn 3 1 r/w 0 tcorn 0 1 r/w 2 tcorn 2 1 r/w 1 tcorn 1 1 r/w n = a or b bit initial value read/write 7 tcntv 7 0 r/w 6 tcntv 6 0 r/w 5 tcntv 5 0 r/w 4 tcntv 4 0 r/w 3 tcntv 3 0 r/w 0 tcntv 0 0 r/w 2 tcntv 2 0 r/w 1 tcntv 1 0 r/w 198 3. timer control register v0 (tcrv0) tcrv0 is an 8-bit read/write register that selects the tcntv input clock, controls the clearing of tcntv, and enables interrupts. tcrv0 is initialized to h'00 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. bit 7: compare match interrupt enable b (cmieb) bit 7 enables or disables the interrupt request (cmib) generated from cmfb when cmfb is set to 1 in tcsrv. bit 7 cmieb description 0 interrupt request (cmib) from cmfb disabled (initial value) 1 interrupt request (cmib) from cmfb enabled bit 6: compare match interrupt enable a (cmiea) bit 6 enables or disables the interrupt request (cmia) generated from cmfa when cmfa is set to 1 in tcsrv. bit 6 cmiea description 0 interrupt request (cmia) from cmfa disabled (initial value) 1 interrupt request (cmia) from cmfa enabled bit 5: timer overflow interrupt enable (ovie) bit 5 enables or disables the interrupt request (ovi) generated from ovf when ovf is set to 1 in tcsrv. bit 5 ovie description 0 interrupt request (ovi) from ovf disabled (initial value) 1 interrupt request (ovi) from ovf enabled bit initial value read/write 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 199 bits 4 and 3: counter clear 1 and 0 (cclr1, cclr0) bits 4 and 3 specify whether or not to clear tcntv, and select compare match a or b or an external reset input. when clearing is specified, if trge is set to 1 in tcrv1, then when tcntv is cleared it is also halted. counting resumes when a trigger edge is input at the trgv pin. if trge is cleared to 0, after tcntv is cleared it continues counting up. bit 4 bit 3 cclr1 cclr0 description 0 0 clearing is disabled (initial value) 0 1 cleared by compare match a 1 0 cleared by compare match b 1 1 cleared by rising edge of external reset input bits 2 to 0: clock select 2 to 0 (cks2 to cks0) bits 2 to 0 and bit icks0 in tcrv1 select the clock input to tcntv. six internal clock sources divided from the system clock (? can be selected. the counter increments on the falling edge. if the external clock is selected, there is a further selection of incrementing on the rising edge, falling edge, or both edges. if trge is cleared to 0, after tcntv is cleared it continues counting up. tcrv0 tcrv1 bit 2 bit 1 bit 0 bit 0 cks2 cks1 cks0 icks0 description 0 0 0 clock input disabled (initial value) 0 0 1 0 internal clock: ?4, falling edge 0 0 1 1 internal clock: ?8, falling edge 0 1 0 0 internal clock: ?16, falling edge 0 1 0 1 internal clock: ?32, falling edge 0 1 1 0 internal clock: ?64, falling edge 0 1 1 1 internal clock: ?128, falling edge 1 0 0 clock input disabled 1 0 1 external clock: rising edge 1 1 0 external clock: falling edge 1 1 1 external clock: rising and falling edges 200 4. timer control/status register v (tcsrv) tcsrv is an 8-bit register that sets compare match flags and the timer overflow flag, and controls compare match output. tcsrv is initialized to h'10 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. bit 7: compare match flag b (cmfb) bit 7 is a status flag indicating that tcntv has matched tcorb. this flag is set by hardware and cleared by software. it cannot be set by software. bit 7 cmfb description 0 clearing conditions: (initial value) after reading cmfb = 1, cleared by writing 0 to cmfb 1 setting conditions: set when the tcntv value matches the tcorb value bit 6: compare match flag a (cmfa) bit 6 is a status flag indicating that tcntv has matched tcora. this flag is set by hardware and cleared by software. it cannot be set by software. bit 6 cmfa description 0 clearing conditions: (initial value) after reading cmfa = 1, cleared by writing 0 to cmfa 1 setting conditions: set when the tcntv value matches the tcora value bit initial value read/write 7 cmfb 0 r/(w) 6 cmfa 0 r/(w) 5 ovf 0 r/(w) 4 ? 1 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w * * * note: * bits 7 to 5 can be only written with 0, for flag clearing. 201 bit 5: timer overflow flag (ovf) bit 5 is a status flag indicating that tcntv has overflowed from h'ff to h'00. this flag is set by hardware and cleared by software. it cannot be set by software. bit 5 ovf description 0 clearing conditions: (initial value) after reading ovf = 1, cleared by writing 0 to ovf 1 setting conditions: set when tcntv overflows from h'ff to h'00 bit 4: reserved bit bit 4 is reserved; it is always read as 1, and cannot be modified. bits 3 to 0: output select 3 to 0 (os3 to os0) bits 3 to 0 select the way in which the output level at the tmov pin changes in response to compare match between tcntv and tcora or tcorb. os3 and os2 select the output level for compare match b. os1 and os0 select the output level for compare match a. the two levels can be controlled independently. if two compare matches occur simultaneously, any conflict between the settings is resolved according to the following priority order: toggle output > 1 output > 0 output. when os3 to os0 are all cleared to 0, timer output is disabled. after a reset, the timer output is 0 until the first compare match. bit 3 bit 2 os3 os2 description 0 0 no change at compare match b (initial value) 0 1 0 output at compare match b 1 0 1 output at compare match b 1 1 output toggles at compare match b bit 1 bit 0 os1 os0 description 0 0 no change at compare match a (initial value) 0 1 0 output at compare match a 1 0 1 output at compare match a 1 1 output toggles at compare match a 202 5. timer control register v1 (tcrv1) tcrv1 is an 8-bit read/write register that selects the valid edge at the trgv pin, enables trgv input, and selects the clock input to tcntv. tcrv1 is initialized to h'e2 upon reset and in watch mode, subsleep mode, and subactive mode. bits 7 to 5: reserved bits bit 7 to 5 are reserved; they are always read as 1, and cannot be modified. bits 4 and 3: trgv input edge select (tveg1, tveg0) bits 4 and 3 select the trgv input edge. bit 4 bit 3 tveg1 tveg0 description 0 0 trgv trigger input is disabled (initial value) 0 1 rising edge is selected 1 0 falling edge is selected 1 1 rising and falling edges are both selected bit 2: trgv input enable (trge) bit 2 enables tcntv counting to be triggered by input at the trgv pin, and enables tcntv counting to be halted when tcntv is cleared by compare match. tcntv stops counting when trge is set to 1, then starts counting when the edge selected by bits tveg1 and tveg0 is input at the trgv pin. bit 2 trge description 0 tcntv counting is not triggered by input at the trgv pin, and does not stop when tcntv is cleared by compare match (initial value) 1 tcntv counting is triggered by input at the trgv pin, and stops when tcntv is cleared by compare match bit initial value read/write 7 ? 1 6 1 5 ? 1 4 tveg1 0 r/w 3 tveg0 0 r/w 0 icks0 0 r/w 2 trge 0 r/w 1 ? 1 203 bit 1: reserved bit bit 1 is reserved; it is always read as 1, and cannot be modified. bit 0: internal clock select 0 (icks0) bit 0 and bits cks2 to cks0 in tcrv0 select the tcntv clock source. for details see 9.8.2 (3), timer control register v0. 9.8.3 timer operation 1. timer v operation a reset initializes tcntv to h'00, tcora and tcorb to h'ff, tcrv0 to h'00, tcsrv to h'10, and tcrv1 to h'e2. timer v can be clocked by one of six internal clocks output from prescaler s, or an external clock, as selected by bits cks2 to cks0 in tcrv0 and bit icks0 in tcrv1. the valid edge or edges of the external clock can also be selected by cks2 to cks0. when the clock source is selected, tcntv starts counting the selected clock input. the tcntv contents are always compared with tcora and tcorb. when a match occurs, the cmfa or cmfb bit is set to 1 in tcsrv. if cmiea or cmieb is set to 1 in tcrv0, a cpu interrupt is requested. at the same time, the output level selected by bits os3 to os0 in tcsrv is output from the tmov pin. when tcnt overflows from h'ff to h'00, if ovie is 1 in tcrv0, a cpu interrupt is requested. if bits cclr1 and cclr0 in tcrv0 are set to 01 (clear by compare match a) or 10 (clear by compare match b), tcntv is cleared by the corresponding compare match. if these bits are set to 11, tcntv is cleared by input of a rising edge at the tmriv pin. if bit trge is set to 1 in tcrv1, when tcntv is cleared by the event selected by bits cclr1 and cclr0, it is also halted. tcntv starts counting when the signal edge selected by bits tveg1 and tveg0 in tcrv1 is input at the trgv pin. 204 2. tcntv increment timing tcntv is incremented by an input (internal or external) clock. internal clock one of six clocks (?128, ?64, ?32, ?16, ?8, ?4) divided from the system clock (? can be selected by bits cks2 to cks0 in tcrv0 and bit icks0 in tcrv1. figure 9-8-2 shows the timing. figure 9-8-2 increment timing with internal clock external clock incrementation on the rising edge, falling edge, or both edges of the external clock can be selected by bits cks2 to cks0 in tcrv0. the external clock pulse width should be at least 1.5 system clocks (? when a single edge is counted, and at least 2.5 system clocks when both edges are counted. shorter pulses will not be counted correctly. figure 9-8-3 shows the timing when both the rising and falling edges of the external clock are selected. n ?1 tcntv input tcntv internal clock n n ?1 205 figure 9-8-3 increment timing with external clock 3. overflow flag set timing the overflow flag (ovf) is set to 1 when tcntv overflows from h'ff to h'00. figure 9-8-4 shows the timing. figure 9-8-4 ovf set timing h'ff h'00 overflow signal tcntv n ?1 n n ?1 tcntv input clock tcntv tmciv (external clock input pin) 206 4. compare match flag set timing compare match flag a or b (cmfa or cmfb) is set to 1 when tcntv matches tcora or tcorb. the internal compare-match signal is generated in the last state in which the values match (when tcntv changes from the matching value to a new value). accordingly, when tcntv matches tcora or tcorb, the compare match signal is not generated until the next clock input to tcntv. figure 9-8-5 shows the timing. figure 9-8-5 cmfa and cmfb set timing 5. tmov output timing the tmov output responds to compare match a or b by remaining unchanged, changing to 0, changing to 1, or toggling, as selected by bits os3 to os0 in tcsrv. figure 9-8-6 shows the timing when the output is toggled by compare match a. figure 9-8-6 tmov output timing timer v output pin compare match a tcora or tcorb compare match signal tcntv n n n + 1 cmfa or cmfb 207 6. tcntv clear timing by compare match tcntv can be cleared by compare match a or b, as selected by bits cclr1 and cclr0 in tcrv0. figure 9-8-7 shows the timing. figure 9-8-7 clear timing by compare match 7. tcntv clear timing by tmriv tcntv can be cleared by a rising edge at the tmriv pin, as selected by bits cclr1 and cclr0 in tcrv0. a tmriv input pulse width of at least 1.5 system clocks is necessary. figure 9-8-8 shows the timing. figure 9-8-8 clear timing by tmriv input timer v output pin tcntv compare match a signal n ?1 n h'00 tcntv compare match a signal n h'00 208 9.8.4 timer v operation modes table 9-7-4 summarizes the timer v operation states. table 9-7-4 timer v operation states sub- sub- operation mode reset active sleep watch active sleep standby tcntv reset functions functions reset reset reset reset tcrv0, tcrv1 reset functions functions reset reset reset reset tcora, tcorb reset functions functions reset reset reset reset tcsrv reset functions functions reset reset reset reset 9.8.5 interrupt sources timer v has three interrupt sources: cmia, cmib, and ovi. table 9-8-4 lists the interrupt sources and their vector address. each interrupt source can be enabled or disabled by an interrupt enable bit in tcrv0. although all three interrupts share the same vector, they have individual interrupt flags, so software can discriminate the interrupt source. table 9-8-4 timer v interrupt sources interrupt description vector address cmia generated from cmfa h'0022 cmib generated from cmfb ovi generated from ovf 209 9.8.6 application examples 1. pulse output with arbitrary duty cycle figure 9-8-9 shows an example of output of pulses with an arbitrary duty cycle. to set up this output: clear bit cclr1 to 0 and set bit cclr0 to 1 in tcrv0 so that tcntv will be cleared by compare match with tcora. set bits os3 to os0 to 0110 in tcsrv so that the output will go to 1 at compare match with tcora and to 0 at compare match with tcorb. set bits cks2 to cks0 in tcrv0 and bit icks0 in tcrv1 to select the desired clock source. with these settings, a waveform is output without further software intervention, with a period determined by tcora and a pulse width determined by tcorb. figure 9-8-9 pulse output example 2. single-shot output with arbitrary pulse width and delay from trgv input the trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the trgv input, as shown in figure 9-8-10. to set up this output: set bit cclr1 to 1 and clear bit cclr0 to 0 in tcrv0 so that tcntv will be cleared by compare match with tcorb. set bits os3 to os0 to 0110 in tcsrv so that the output will go to 1 at compare match with tcora and to 0 at compare match with tcorb. set bits tveg1 and tveg0 to 10 in tcrv1 and set trge to 1 to select the falling edge of the trgv input. set bits cks2 to cks0 in tcrv0 and bit icks0 in tcrv1 to select the desired clock source. tcntv counter cleared h'ff tcora tcorb h'00 tmov 210 after these settings, a pulse waveform will be output without further software intervention, with a delay determined by tcora from the trgv input, and a pulse width determined by (tcorb tcora). figure 9-8-10 pulse output synchronized to trgv input counter cleared tcntv compare match a compare match b clears and halts tcntv compare match a compare match b clears and halts tcntv h'ff tcorb tcora h'00 trgv tmov 211 9.8.7 application notes the following types of contention can occur in timer v operation. 1. contention between tcntv write and counter clear if a tcntv clear signal is generated in the t 3 state of a tcntv write cycle, clearing takes precedence and the write to the counter is not carried out. figure 9-8-11 shows the timing. figure 9-8-11 contention between tcntv write and clear t 1 t 2 t 3 tcntv write cycle by cpu address tcntv address internal write signal counter clear signal tcntv n h'00 212 2. contention between tcntv write and increment if a tcntv increment clock signal is generated in the t 3 state of a tcntv write cycle, the write takes precedence and the counter is not incremented. figure 9-8-12 shows the timing. figure 9-8-12 contention between tcntv write and increment t 1 t 2 t 3 tcntv write cycle by cpu address internal write signal tcntv clock tcntv n m tcntv write data tcntv address 213 3. contention between tcor write and compare match if a compare match is generated in the t 3 state of a tcora or tcorb write cycle, the write to tcora or tcorb takes precedence and the compare match signal is inhibited. figure 9-8-13 shows the timing. figure 9-8-13 contention between tcora write and compare match t 1 t 2 t 3 tcora write cycle by cpu address internal write signal tcntv tcora n m tcora write data tcora address n n + 1 compare match signal inhibited 214 4. contention between compare match a and b if compare match a and b occur simultaneously, any conflict between the output selections for compare match a and compare match b is resolved by following the priority order in table 9-8-5. table 9-8-5 timer output priority order output setting priority toggle output high 1 output 0 output no change low 5. internal clock switching and counter operation depending on the timing, tcntv may be incremented by a switch between different internal clock sources. table 9-8-6 shows the relation between internal clock switchover timing (by writing to bits cks1 and cks0) and tcntv operation. when tcntv is internally clocked, an increment pulse is generated from the falling edge of an internal clock signal, which is divided from the system clock (?. for this reason, in a case like no. 3 in table 9-8-6 where the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing tcntv to increment. tcntv can also be incremented by a switch between internal and external clocks. 215 table 9-8-6 internal clock switching and tcntv operation clock levels before and after modifying no. bits cks1 and cks0 tcntv operation 1 goes from low level to low level* 1 2 goes from low to high * 2 notes: 1. including a transition from the low level to the stopped state, or from the stopped state to the low level. 2. including a transition from the stopped state to the high level. 216 n + 1 clock before switching clock after switching count clock tcntv write to cks1 and cks0 n n + 1 n + 2 clock before switching clock after switching count clock tcntv write to cks1 and cks0 n table 9-8-6 internal clock switching and tcntv operation (cont) clock levels before and after modifying no. bits cks1 and cks0 tcntv operation 3 goes from high level to low level * 1 4 goes from high to high notes: 1. including a transition from the high level to the stopped state. 2. the switchover is seen as a falling edge, and tcntv is incremented. 217 n + 1 n n + 2 * 2 clock before switching clock after switching count clock tcntv write to cks1 and cks0 n +1 n +2 n clock before switching clock after switching count clock write to cks1 and cks0 tcntv 9.9 timer x 9.9.1 overview timer x is based on a 16-bit free-running counter (frc). it can output two independent waveforms, or measure input pulse widths and external clock periods. 1. features features of timer x are given below. choice of three internal clock sources (?2, ?8, ?32) or an external clock (can be used as an external event counter). two independent output compare waveforms. four independent input capture channels, with selection of rising or falling edge and buffering option. counter can be cleared by compare match a. seven independent interrupt sources: two compare match, four input capture, one overflow 218 2. block diagram figure 9-9-1 shows a block diagram of timer x. figure 9-9-1 block diagram of timer x ftoa ftob timer interrupt enable register timer control/status register x free-running counter output compare register a output compare register b timer control register x timer output compare control register input capture register a input capture register b input capture register c input capture register d prescaler s notation: tier: tcsrx: frc: ocra: ocrb: tcrx: tocr: icra: icrb: icrc: icrd: pss: interrupt request input capture control internal data bus comparator comparator icra icrc icrb icrd tcrx ocrb ocra tocr frc tcsrx tier pss ftia ftib ftic ftid ftci 219 3. pin configuration table 9-9-1 shows the timer x pin configuration. table 9-9-1 pin configuration name abbrev. i/o function counter clock input ftci input clock input to frc output compare a ftoa output output pin for output compare a output compare b ftob output output pin for output compare b input capture a ftia input input pin for input capture a input capture b ftib input input pin for input capture b input capture c ftic input input pin for input capture c input capture d ftid input input pin for input capture d 220 4. register configuration table 9-9-2 shows the register configuration of timer x. table 9-9-2 timer x registers name abbrev. r/w initial value address timer interrupt enable register tier r/w h'01 h'f770 timer control/status register x tcsrx r/(w) * 1 h'00 h'f771 free-running counter h frch r/w h'00 h'f772 free-running counter l frcl r/w h'00 h'f773 output compare register ah ocrah r/w h'ff h'f774 * 2 output compare register al ocral r/w h'ff h'f775 * 2 output compare register bh ocrbh r/w h'ff h'f774 * 2 output compare register bl ocrbl r/w h'ff h'f775 * 2 timer control register x tcrx r/w h'00 h'f776 timer output compare control tocr r/w h'e0 h'f777 register input capture register ah icrah r h'00 h'f778 input capture register al icral r h'00 h'f779 input capture register bh icrbh r h'00 h'f77a input capture register bl icrbl r h'00 h'f77b input capture register ch icrch r h'00 h'f77c input capture register cl icrcl r h'00 h'f77d input capture register dh icrdh r h'00 h'f77e input capture register dl icrdl r h'00 h'f77f notes: 1. bits 7 to 1 can only be written with 0 for flag clearing. bit 0 is a read/write bit. 2. ocra and ocrb share the same address. they are selected by the ocrs bit in tocr. 221 9.9.2 register descriptions 1. free-running counter (frc) free-running counter h (frch) free-running counter l (frcl) frc is a 16-bit read/write up-counter, which is incremented by internal or external clock input. the clock source is selected by bits cks1 and cks0 in tcrx. frc can be cleared by compare match a, depending on the setting of cclra in tcsrx. when frc overflows from h'ffff to h'0000, ovf is set to 1 in tcsrx. if ovie = 1 in tier, a cpu interrupt is requested. frc can be written and read by the cpu. since frc has 16 bits, data is transferred between the cpu and frc via a temporary register (temp). for details see 9.9.3, cpu interface. frc is initialized to h'0000 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. 2. output compare registers a and b (ocra, ocrb) output compare registers ah and bh (ocrah, ocrbh) output compare registers al and bl (ocral, ocrbl) there are two 16-bit read/write output compare registers, ocra and ocrb, the contents of which are always compared with frc. when the values match, ocfa or ocfb is set to 1 in tcsrx. if ociae = 1 or ocibe = 1 in tier, a cpu interrupt is requested. bit initial value read/write 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w ocrah, ocrbh ocral, ocrbl ocra, ocrb bit initial value read/write 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w frch frcl frc 222 when a compare match with ocra or ocrb occurs, if oea = 1 or oeb = 1 in tocr, the value selected by olvla or olvlb in tocr is output at the ftoa or ftob pin. after a reset, the output from the ftoa or ftob pin is 0 until the first compare match occurs. ocra and ocrb can be written and read by the cpu. since they are 16-bit registers, data is transferred between them and the cpu via a temporary register (temp). for details see 9.9.3, cpu interface. ocra and ocrb are initialized to h'ffff upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. 3. input capture registers a to d (icra to icrd) input capture registers ah to dh (icrah to icrdh) input capture registers al to dl (icral to icrdl) there are four 16-bit read only input capture registers, icra to icrd. when the designated edge of an input capture signal is input, the frc value is transferred to the corresponding input capture register, and the corresponding input capture flag (icfa to icfd) is set to 1 in tcsrx. if the corresponding input capture interrupt enable bit (iciae to icide) is 1 in tier, a cpu interrupt is requested. the valid edge of the input signal can be selected by bits iedga to iedgd in tcrx. icrc and icrd can also be used as buffer registers for icra and icrb. buffering is enabled by bits bufea and bufeb in tcrx. figure 9-9-2 shows the interconnections when icrc operates as a buffer register of icra (when bufea = 1). in buffered input capture operations, both the rising and falling edges of the external input signal can be selected simultaneously, by setting iedga iedgc. if iedga = iedgc, then only one edge is selected (either the rising edge or falling edge). see table 9-9-3. note: the frc value is transferred to the input capture register (icr) regardless of the value of the input capture flag (icf). bit initial value read/write 15 0 r 14 0 r 13 0 r 12 0 r 11 0 r 10 0 r 9 0 r 8 0 r 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r icrah, icrbh, icrch, icrdh icral, icrbl, icrcl, icrdl icra, icrb, icrc, icrd 223 figure 9-9-2 buffer operation (example) table 9-9-3 input edge selection during buffer operation iedga iedgc input edge selection 0 0 falling edge of input capture a input signal is captured (initial value) 0 1 rising and falling edge of input capture a input signal are both captured 1 0 1 1 rising edge of input capture a input signal is captured icra to icrd can be written and read by the cpu. since they are 16-bit registers, data is transferred from them to the cpu via a temporary register (temp). for details see 9.9.3, cpu interface. to assure input capture, the pulse width of the input capture input signal must be at least 1.5 system clocks (? when a single edge is selected, or at least 2.5 system clocks (? when both edges are selected. icra to icrd are initialized to h'0000 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. edge detector and internal capture signal generator icrc icra frc ftia ieoga bufea iedgc 224 4. timer interrupt enable register (tier) tier is an 8-bit read/write register that enables or disables interrupt requests. tier is initialized to h'01 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. bit 7: input capture interrupt a enable (iciae) bit 7 enables or disables the icia interrupt requested when icfa is set to 1 in tcsrx. bit 7 iciae description 0 interrupt request by icfa (icia) is disabled (initial value) 1 interrupt request by icfa (icia) is enabled bit 6: input capture interrupt b enable (icibe) bit 6 enables or disables the icib interrupt requested when icfb is set to 1 in tcsrx. bit 6 icibe description 0 interrupt request by icfb (icib) is disabled (initial value) 1 interrupt request by icfb (icib) is enabled bit 5: input capture interrupt c enable (icice) bit 5 enables or disables the icic interrupt requested when icfc is set to 1 in tcsrx. bit 5 icice description 0 interrupt request by icfc (icic) is disabled (initial value) 1 interrupt request by icfc (icic) is enabled bit initial value read/write 7 iciae 0 r/w 6 icibe 0 r/w 5 icice 0 r/w 4 icide 0 r/w 3 ociae 0 r/w 0 ? 1 2 ocibe 0 r/w 1 ovie 0 r/w 225 bit 4: input capture interrupt d enable (icide) bit 4 enables or disables the icid interrupt requested when icfd is set to 1 in tcsrx. bit 4 icide description 0 interrupt request by icfd (icid) is disabled (initial value) 1 interrupt request by icfd (icid) is enabled bit 3: output compare interrupt a enable (ociae) bit 3 enables or disables the ocia interrupt requested when ocfa is set to 1 in tcsrx. bit 3 ociae description 0 interrupt request by ocfa (ocia) is disabled (initial value) 1 interrupt request by ocfa (ocia) is enabled bit 2: output compare interrupt b enable (ocibe) bit 2 enables or disables the ocib interrupt requested when ocfb is set to 1 in tcsrx. bit 2 ocibe description 0 interrupt request by ocfb (ocib) is disabled (initial value) 1 interrupt request by ocfb (ocib) is enabled bit 1: timer overflow interrupt enable (ovie) bit 1 enables or disables the fovi interrupt requested when ovf is set to 1 in tcsrx. bit 1 ovie description 0 interrupt request by ovf (fovi) is disabled (initial value) 1 interrupt request by ovf (fovi) is enabled bit 0: reserved bit bit 0 is reserved; it is always read as 1, and cannot be modified. 226 5. timer control/status register x (tcsrx) tcsrx is an 8-bit register that selects clearing of the counter and controls interrupt request signals. tcsrx is initialized to h'00 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. other timing is described in section 9-9-4, timer operation. bit 7: input capture flag a (icfa) bit 7 is a status flag that indicates that the frc value has been transferred to icra by an input capture signal. if bufea is set to 1 in tcrx, icfa indicates that the frc value has been transferred to icra by an input capture signal and that the icra value before this update has been transferred to icrc. this flag is set by hardware and cleared by software. it cannot be set by software. bit 7 icfa description 0 clearing conditions: (initial value) after reading icfa = 1, cleared by writing 0 to icfa 1 setting conditions: set when the frc value is transferred to icra by an input capture signal bit 6: input capture flag b (icfb) bit 6 is a status flag that indicates that the frc value has been transferred to icrb by an input capture signal. if bufeb is set to 1 in tcrx, icfb indicates that the frc value has been transferred to icrb by an input capture signal and that the icrb value before this update has been transferred to icrd. this flag is set by hardware and cleared by software. it cannot be set by software. bit 6 icfb description 0 clearing conditions: (initial value) after reading icfb = 1, cleared by writing 0 to icfb 1 setting conditions: set when the frc value is transferred to icrb by an input capture signal bit initial value read/write 7 icfa 0 r/(w) 6 icfb 0 r/(w) 5 icfc 0 r/(w) 4 icfd 0 r/(w) 3 ocfa 0 r/(w) 0 cclra 0 r/w 2 ocfb 0 r/(w) 1 ovf 0 r/(w) * * * note: * bits 7 to 1 can only be written with 0 for flag clearing. * * * * 227 bit 5: input capture flag c (icfc) bit 5 is a status flag that indicates that the frc value has been transferred to icrc by an input capture signal. if bufea is set to 1 in tcrx, icfc is set by the input capture signal even though the frc value is not transferred to icrc. in buffered operation, icfc can accordingly be used as an external interrupt, by setting the icice bit to 1. this flag is set by hardware and cleared by software. it cannot be set by software. bit 5 icfc description 0 clearing conditions: (initial value) after reading icfc = 1, cleared by writing 0 to icfc 1 setting conditions: set by input capture signal bit 4: input capture flag d (icfd) bit 4 is a status flag that indicates that the frc value has been transferred to icrd by an input capture signal. if bufeb is set to 1 in tcrx, icfd is set by the input capture signal even though the frc value is not transferred to icrd. in buffered operation, icfd can accordingly be used as an external interrupt, by setting the icide bit to 1. this flag is set by hardware and cleared by software. it cannot be set by software. bit 4 icfd description 0 clearing conditions: (initial value) after reading icfd = 1, cleared by writing 0 to icfd 1 setting conditions: set by input capture signal bit 3: output compare flag a (ocfa) bit 3 is a status flag that indicates that the frc value has matched ocra. this flag is set by hardware and cleared by software. it cannot be set by software. bit 3 ocfa description 0 clearing conditions: (initial value) after reading ocfa = 1, cleared by writing 0 to ocfa 1 setting conditions: set when frc matches ocra 228 bit 2: output compare flag b (ocfb) bit 2 is a status flag that indicates that the frc value has matched ocrb. this flag is set by hardware and cleared by software. it cannot be set by software. bit 2 ocfb description 0 clearing conditions: (initial value) after reading ocfb = 1, cleared by writing 0 to ocfb 1 setting conditions: set when frc matches ocrb bit 1: timer overflow flag (ovf) bit 1 is a status flag that indicates that frc has overflowed from h'ffff to h'0000. this flag is set by hardware and cleared by software. it cannot be set by software. bit 1 ovf description 0 clearing conditions: (initial value) after reading ovf = 1, cleared by writing 0 to ovf 1 setting conditions: set when the frc value overflows from h'ffff to h'0000 bit 0: counter clear a (cclra) bit 0 selects whether or not to clear frc by compare match a (when frc matches ocra). bit 0 cclra description 0 frc is not cleared by compare match a (initial value) 1 frc is cleared by compare match a 229 6. timer control register x (tcrx) tcrx is an 8-bit read/write register that selects the valid edges of the input capture signals, enables buffering, and selects the frc clock source. tcrx is initialized to h'00 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. bit 7: input edge select a (iedga) bit 7 selects the rising or falling edge of the input capture a input signal (ftia). bit 7 iedga description 0 falling edge of input a is captured (initial value) 1 rising edge of input a is captured bit 6: input edge select b (iedgb) bit 6 selects the rising or falling edge of the input capture b input signal (ftib). bit 6 iedgb description 0 falling edge of input b is captured (initial value) 1 rising edge of input b is captured bit 5: input edge select c (iedgc) bit 5 selects the rising or falling edge of the input capture c input signal (ftic). bit 5 iedgc description 0 falling edge of input c is captured (initial value) 1 rising edge of input c is captured bit initial value read/write 7 iedga 0 r/w 6 iedgb 0 r/w 5 iedgc 0 r/w 4 iedgd 0 r/w 3 bufea 0 r/w 0 cks0 0 r/w 2 bufeb 0 r/w 1 cks1 0 r/w 230 bit 4: input edge select d (iedgd) bit 4 selects the rising or falling edge of the input capture d input signal (ftid). bit 4 iedgd description 0 falling edge of input d is captured (initial value) 1 rising edge of input d is captured bit 3: buffer enable a (bufea) bit 3 selects whether or not to use icrc as a buffer register for icra. bit 3 bufea description 0 icrc is not used as a buffer register for icra (initial value) 1 icrc is used as a buffer register for icra bit 2: buffer enable b (bufeb) bit 2 selects whether or not to use icrd as a buffer register for icrb. bit 2 bufeb description 0 icrd is not used as a buffer register for icrb (initial value) 1 icrd is used as a buffer register for icrb bits 1 and 0: clock select (cks1, cks0) bits 1 and 0 select one of three internal clock sources or an external clock for input to frc. the external clock is counted on the rising edge. bit 1 bit 0 cks1 cks0 description 0 0 internal clock: /2 (initial value) 0 1 internal clock: /8 1 0 internal clock: /32 1 1 external clock: rising edge 231 7. timer output compare control register (tocr) tocr is an 8-bit read/write register that selects the output compare output levels, enables output compare output, and controls access to ocra and ocrb. tocr is initialized to h'e0 upon reset and in standby mode, watch mode, subsleep mode, and subactive mode. bits 7 to 5: reserved bits bit 7 to 5 are reserved; they are always read as 1, and cannot be modified. bit 4: output compare register select (ocrs) ocra and ocrb share the same address. ocrs selects which register is accessed when this address is written or read. it does not affect the operation of ocra and ocrb. bit 4 ocrs description 0 ocra is selected (initial value) 1 ocrb is selected bit 3: output enable a (oea) bit 3 enables or disables the timer output controlled by output compare a. bit 3 oea description 0 output compare a output is disabled (initial value) 1 output compare a output is enabled bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 4 ocrs 0 r/w 3 oea 0 r/w 0 olvlb 0 r/w 2 oeb 0 r/w 1 olvla 0 r/w 232 bit 2: output enable b (oeb) bit 2 enables or disables the timer output controlled by output compare b. bit 2 oeb description 0 output compare b output is disabled (initial value) 1 output compare b output is enabled bit 1: output level a (olvla) bit 1 selects the output level that is output at pin ftoa by compare match a (when frc matches ocra). bit 1 olvla description 0 low level (initial value) 1 high level bit 0: output level b (olvlb) bit 0 selects the output level that is output at pin ftob by compare match b (when frc matches ocrb). bit 0 olvlb description 0 low level (initial value) 1 high level 9.9.3 cpu interface frc, ocra, ocrb, and icra to icrd are 16-bit registers, but the cpu is connected to the on- chip peripheral modules by an 8-bit data bus. when the cpu accesses these registers, it therefore uses an 8-bit temporary register (temp). these registers should always be accessed 16 bits at a time. if two consecutive byte-size mov instructions are used, the upper byte must be accessed first and the lower byte second. data will not be transferred correctly if only the upper byte or only the lower byte is accessed. 233 1. write access write access to the upper byte results in transfer of the upper-byte write data to temp. next, write access to the lower byte results in transfer of the data in temp to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte. figure 9-9-3 shows an example of the writing of h'aa55 to frc. figure 9-9-3 write access to frc (cpu ? frc) cpu (h'aa) write to upper byte write to lower byte cpu (h'55) bus interface bus interface module data bus module data bus temp (h'aa) frch ( ) frcl ( ) temp (h'aa) frch (h'aa) frcl (h'55) 234 2. read access in access to frc and icra to icrd, when the upper byte is read the upper-byte data is transferred directly to the cpu and the lower-byte data is transferred to temp. next, when the lower byte is read, the lower-byte data in temp is transferred to the cpu. in access to ocra or ocrb, when the upper byte is read the upper-byte data is transferred directly to the cpu, and when the lower byte is read the lower-byte data is transferred directly to the cpu. figure 9-9-4 shows an example of the reading of frc when frc contains h'aaff. figure 9-9-4 read access to frc (frc ? cpu) cpu (h'aa) read upper byte read lower byte cpu (h'ff) bus interface bus interface module data bus module data bus temp (h'ff) frch (h'aa) frcl (h'ff) temp (h'ff) frch ( ab ) frcl ( 00 ) note: * h'ab00 if counter has been updated once. 235 9.9.4 timer operation 1. timer operation output compare operation following a reset, frc is initialized to h'0000 and starts counting up. bits cks1 and cks0 in tcrx can select one of three internal clock sources or an external clock for input to frc. the frc contents are compared constantly with ocra and ocrb. when a match occurs, the output at pin ftoa or ftob goes to the level selected by olvla or olvlb in tocr. following a reset, the output at both ftoa and ftob is 0 until the first compare match. if cclra is set to 1 in tcsrx, compare match a clears frc to h'0000. input capture operation following a reset, frc is initialized to h'0000 and starts counting up. bits cks1 and cks0 in tcrx can select one of three internal clock sources or an external clock for input to frc. when the edges selected by bits iedga to iedgd in tcrx are input at pins ftia to ftid, the frc value is transferred to icra to icrd, and icfa to icfd are set in tcsrx. if bits iciae to icide are set to 1 in tier, a cpu interrupt is requested. if bits bufea and bufeb are set to 1 in tcrx, icrc and icrd operate as buffer registers for icra or icrb. when the edges selected by bits iedga to iedgd in tcrx are input at pins ftia and ftib, the frc value is transferred to icra or icrb, and the previous value in icra or icrb is transferred to icrc or icrd. simultaneously, icfa or icfb is set in tcsrx. if bit iciae or icibe is set to 1 in tier, a cpu interrupt is requested. 236 2. frc count timing frc is incremented by clock input. bits cks1 and cks0 in tcrx can select one of three internal clock sources (?2, ?8, ?32) or an external clock. internal clock bits cks1 and cks0 in tcrx select one of three internal clock sources (?2, ?8, ?32) created by dividing the system clock (?. figure 9-9-5 shows the increment timing. figure 9-9-5 increment timing with internal clock n ?1 frc input clock frc internal clock n n + 1 237 external clock external clock input is selected when bits cks1 and cks0 are both set to 1 in tcrx. frc increments on the rising edge of the external clock. an external pulse width of at least 1.5 system clocks (? is necessary. shorter pulses will not be counted correctly. figure 9-9-6 shows the timing. figure 9-9-6 increment timing with external clock n ?1 n frc input clock frc ftci (external clock input pin) 238 3. output compare timing when a compare match occurs, the output level selected by the olvl bit in tocr is output at pin ftoa or ftob. figure 9-9-7 shows the output timing for output compare a. figure 9-9-7 output compare a output timing n + 1 n n + 1 n n ocra compare match a signal frc olvla ftoa (output compare a output pin) clear * note: * by execution of a software instruction. 239 4. frc clear timing frc can be cleared by compare match a. figure 9-9-8 shows the timing. figure 9-9-8 clear timing by compare match a 5. input capture timing input capture timing the rising or falling edge is selected for input capture by bits iedga to iedgd in tcrx. figure 9-9-9 shows the timing when the rising edge is selected (iedga/b/c/d = 1). figure 9-9-9 input capture signal timing (normal case) if the input at the input capture pin occurs while the upper byte of the corresponding input capture register (icra to icrd) is being read, the internal input capture signal is delayed by one system clock (?. figure 9-9-10 shows the timing. internal input capture signal input capture pin n h'0000 frc compare match a signal 240 figure 9-9-10 input capture signal timing (during icra-icrd read) buffered input capture timing input capture can be buffered by using icrc or icrd as a buffer for icra or icrb. figure 9-9-11 shows the timing when icra is buffered by icrc (bufea = 1) and both the rising and falling edges are selected (iedga = 1 and iedgc = 0, or iedga = 0 and iedgc = 1). figure 9-9-11 buffered input capture timing (normal case) n n + 1 n n + 1 m n n n m m m n ftia internal input capture signal frc icra icrc internal input capture signal input capture pin t 1 t 2 t 3 icra-icrd upper byte read cycle 241 when icrc or icrd is used as a buffer register, the input capture flag is still set by the selected edge of the input capture input signal. for example, if icrc is used to buffer icra, when the edge transition selected by the iedgc bit occurs at the input capture pin, icf will be set, and if the iciec bit is set to 1, an interrupt will be requested. the frc value will not be transferred to icrc, however. in buffered operation, if the upper byte of one of the two registers that receives a data transfer (icra and icrc, or icrb and icrd) is being read when an internal input capture signal would normally occur, the internal input capture signal will be delayed by one system clock (?. figure 9-9-12 shows the case when bufea = 1. figure 9-9-12 buffered input capture signal timing (during icra or icrc read) internal input capture signal ftia t 1 t 2 t 3 icra or icrc upper byte read cycle by cpu 242 6. input capture flag (icfa to icfd) set timing figure 9-9-13 shows the timing when an input capture flag (icfa to icfd) is set to 1 and the frc value is transferred to the corresponding input capture register (icra to icrd). figure 9-9-13 icfa to icfd set timing 7. output compare flag (ocfa or ocfb) set timing ocfa and ocfb are set to 1 by internal compare match signals that are output when frc matches ocra or ocrb. the compare match signal is generated in the last state during which the values match (when frc is updated from the matching value to a new value). when frc matches ocra or ocrb, the compare match signal is not generated until the next counter clock. figure 9-9-14 shows the ocfa and ocfb set timing. icfa to icfd frc internal input capture signal n n icra to icrd 243 figure 9-9-14 ocfa and ocfb set timing 8. overflow flag (ovf) set timing ovf is set to 1 when frc overflows from h'ffff to h'0000. figure 9-9-15 shows the timing. figure 9-9-15 ovf set timing h'ffff h'0000 overflow signal frc ovf ocra, ocrb internal compare match signal frc n n + 1 n ocfa, ocfb 244 9.9.5 timer x operation modes figure 9-9-4 shows the timer x operation modes. table 9-9-4 timer x operation modes sub- sub- operation mode reset active sleep watch active sleep standby frc reset functions functions reset reset reset reset ocra, ocrb reset functions functions reset reset reset reset icra to icrd reset functions functions reset reset reset reset tier reset functions functions reset reset reset reset tcrx reset functions functions reset reset reset reset tocr reset functions functions reset reset reset reset tcsrx reset functions functions reset reset reset reset 9.9.6 interrupt sources timer x has three types of interrupts and seven interrupt sources: icia to icid, ocia, ocib, and fovi. table 9-9-5 lists the sources of interrupt requests. each interrupt source can be enabled or disabled by an interrupt enable bit in tier. although all seven interrupts share the same vector, they have individual interrupt flags, so software can discriminate the interrupt source. table 9-9-5 timer x interrupt sources interrupt description vector address icia interrupt requested by icfa h'0020 icib interrupt requested by icfb icic interrupt requested by icfc icid interrupt requested by icfd ocia interrupt requested by ocfa ocib interrupt requested by ocfb fovi interrupt requested by ovf 245 9.9.7 timer x application example figure 9-9-16 shows an example of the output of pulse signals with a 50% duty cycle and arbitrary phase offset. to set up this output: set bit cclra to 1 in tcsrx. have software invert the olvla and olvlb bits at each corresponding compare match. figure 9-9-16 pulse output example tcntv counter cleared h'ffff ocra ocrb h'0000 ftoa ftob 246 9.9.8 application notes the following types of contention can occur in timer x operation. 1. contention between frc write and counter clear if an frc clear signal is generated in the t 3 state of a write cycle to the lower byte of frc, clearing takes precedence and the write to the counter is not carried out. figure 9-9-17 shows the timing. figure 9-9-17 contention between frc write and clear t 1 t 2 t 3 frc lower byte write cycle address frc address internal write signal counter clear signal frc n h'0000 247 2. contention between frc write and increment if an frc increment clock signal is generated in the t 3 state of a write cycle to the lower byte of frc, the write takes precedence and the counter is not incremented. figure 9-9-18 shows the timing. figure 9-9-18 contention between frc write and increment t 1 t 2 t 3 frc lower byte write cycle address internal write signal frc input clock frc n m frc write data frc address 248 3. contention between ocr write and compare match if a compare match is generated in the t 3 state of a write cycle to the lower byte of ocra or ocrb, the write to ocra or ocrb takes precedence and the compare match signal is inhibited. figure 9-9-19 shows the timing. figure 9-9-19 contention between ocr write and compare match t 1 t 2 t 3 ocr lower byte write cycle address internal write signal frc ocr n m write data ocr address n n + 1 internal compare match signal inhibited 249 4. internal clock switching and counter operation depending on the timing, frc may be incremented by a switch between different internal clock sources. table 9-9-6 shows the relation between internal clock switchover timing (by writing to bits cks1 and cks0) and frc operation. when frc is internally clocked, an increment pulse is generated from the falling edge of an internal clock signal, which is divided from the system clock (?. for this reason, in a case like no. 3 in table 9-9-6 where the switch is from a high clock signal to a low clock signal, the switchover is seen as a falling edge, causing frc to increment. frc can also be incremented by a switch between internal and external clocks. table 9-9-6 internal clock switching and frc operation clock levels before and after modifying no. bits cks1 and cks0 frc operation 1 goes from low level to low level 2 goes from low to high 250 n + 1 clock before switching clock after switching count clock frc write to cks1 and cks0 n n + 1 n + 2 clock before switching clock after switching count clock frc write to cks1 and cks0 n table 9-9-6 internal clock switching and frc operation (cont) clock levels before and after modifying no. bits cks1 and cks0 frc operation 3 goes from high level to low level 4 goes from high to high note: * the switchover is seen as a falling edge, and frc is incremented. 251 n + 1 n n + 2 * clock before switching clock after switching count clock frc write to cks1 and cks0 n + 1 n + 2 n clock before switching clock after switching count clock write to cks1 and cks0 frc 9.10 timer y 9.10.1 overview timer y is a 16-bit up-counter that increments each time a clock pulse is input. this timer has two operation modes, interval and auto reload. 1. features features of timer y are given below. choice of seven internal clock sources (?8192, ?2048, ?512, ?256, ?64, ?16, ?4) or an external clock (can be used as an external event counter). an interrupt is requested when the counter overflows. 2. block diagram figure 9-10-1 shows a block diagram of timer y. figure 9-10-1 timer y block diagram pss tmy tcy tly notation: irrty tmy: tcy: tly: irrty: pss: timer mode register y timer counter y timer load register y timer y overflow interrupt request flag prescaler s internal data bus tmiy 252 3. pin configuration table 9-10-1 shows the timer y pin configuration. table 9-10-1 pin configuration name abbrev. i/o function timer y event input tmiy input event input to tcy 4. register configuration table 9-10-2 shows the register configuration of timer y. table 9-10-2 timer y registers name abbrev. r/w initial value address timer mode register y tmy r/w h'78 h'ffcd timer counter yh tcyh r h'00 h'ffce timer counter yl tcyl r h'00 h'ffcf timer load register yh tlyh w h'00 h'ffce timer load register yl tlyl w h'00 h'ffcf 9.10.2 register descriptions 1. timer mode register y (tmy) tmy is an 8-bit read/write register for selecting the auto-reload function and input clock. upon reset, tmy is initialized to h'78. bit initial value read/write 7 tmy7 0 r/w 6 ? 1 5 ? 1 4 ? 1 3 ? 1 0 tmy0 0 r/w 2 tmy2 0 r/w 1 tmy1 0 r/w 253 bit 7: auto-reload function select (tmy7) bit 7 selects whether timer y is used as an interval timer or auto-reload timer. bit 7 tmy7 description 0 interval timer function selected (initial value) 1 auto-reload function selected bits 6 to 3: reserved bits bits 6 to 3 are reserved; they are always read as 1, and cannot be modified. bits 2 to 0: clock select (tmy2 to tmy0) bits 2 to 0 select the clock input to tcy. bit 2 bit 1 bit 0 tmy2 tmy1 tmy0 description 0 0 0 internal clock: ?8192 (initial value) 0 0 1 internal clock: ?2048 0 1 0 internal clock: ?512 0 1 1 internal clock: ?256 1 0 0 internal clock: ?64 1 0 1 internal clock: ?16 1 1 0 internal clock: ?4 1 1 1 external event (tmiy), rising or falling edge * note: * the edge of the external event signal is selected by bit integ7 in interrupt edge select register 2 (iegr2). see 3.3.2 (2), interrupt edge select register 2 (iegr2), for details. 254 2. timer counter y (tcy) timer counter yh (tcyh) timer counter yl (tcyl) tcy is a 16-bit read-only up-counter, which is incremented by internal or external clock input. the clock source for input to this counter is selected by bits tmy2 to tmy0 in timer mode register y (tmy). when tcy overflows from h'ffff to h'0000 or to the value set in tly, the irrty bit in irr1 is set to 1. tcy can always be read by the cpu. since tcy has 16 bits, data is transferred between the cpu and tcy via a temporary register (temp). for details see 9.10.3, cpu interface. tcy is allocated to the same address as tly. upon reset, tcy is initialized to h'0000. bit initial value read/write 15 0 r 14 0 r 13 0 r 12 0 r 11 0 r 10 0 r 9 0 r 8 0 r 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r tcyh tcyl tcy 255 3. timer load register y (tly) timer load register yh (tlyh) timer load register yl (tlyl) tly is a 16-bit write-only register for setting the reload value of tcy. when a reload value is set in tly, the same value is loaded into tcy as well, and tcy starts counting up from that value. when tcy overflows during operation in auto-reload mode, the tly value is loaded into tcy. accordingly, overflow periods can be set within the range of 1 to 65536 input clocks. the same address is allocated to tly as to tcy. upon reset, tly is initialized to h'0000. 9.10.3 cpu interface tcy and tly are 16-bit registers, but the cpu is connected to the on-chip peripheral modules by an 8-bit data bus. when the cpu accesses these registers, it therefore uses an 8-bit temporary register (temp). these registers should always be accessed 16 bits at a time. if two consecutive byte-size mov instructions are used, the upper byte must be accessed first and the lower byte second. data will not be transferred correctly if only the upper byte or only the lower byte is accessed. bit initial value read/write 15 0 w 14 0 w 13 0 w 12 0 w 11 0 w 10 0 w 9 0 w 8 0 w 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 2 0 w 1 0 w 0 0 w tlyh tlyl tly 256 1. write access write access to the upper byte results in transfer of the upper-byte write data to temp. next, write access to the lower byte results in transfer of the data in temp to the upper register byte, and direct transfer of the lower-byte write data to the lower register byte. figure 9-10-2 shows an example of the writing of h'aa55 to tly. figure 9-10-2 write access to tly (cpu ? tly) cpu (h'aa) write to upper byte write to lower byte cpu (h'55) bus interface bus interface module data bus module data bus temp (h'aa) tlyh ( ) tlyl ( ) temp (h'aa) tlyh (h'aa) tlyl (h'55) 257 2. read access when the upper byte is read the upper-byte data is transferred directly to the cpu and the lower- byte data is transferred to temp. next, when the lower byte is read, the lower-byte data in temp is transferred to the cpu. figure 9-10-3 shows an example of the reading of tcy when tcy contains h'aaff. figure 9-10-3 read access to tcy (tcy ? cpu) cpu (h'aa) read upper byte read lower byte cpu (h'ff) bus interface bus interface module data bus module data bus temp (h'ff) tcyh (h'aa) tcyl (h'ff) temp (h'ff) tcyh ( ab ) tcyl ( 00 ) note: * h'ab00 if counter has been updated once. * * 258 9.10.4 timer operation 1. interval timer operation when bit tmy7 in timer mode register y (tmy) is cleared to 0, timer y functions as a 16-bit interval timer. upon reset, tcy is cleared to h'0000 and bit tmy7 is cleared to 0, so up-counting and interval timing resume immediately. the clock input to timer y is selected from seven internal clock signals output by prescaler s or an external clock input at the tmiy pin. the selection is made by bits tmy2 to tmy0 of tmy. after the count value in tcy reaches h'ffff, the next clock signal input causes timer y to overflow, setting bit irrty to 1 in interrupt request register 1 (irr1). if ienty = 1 in interrupt enable register 1 (ienr1), a cpu interrupt is requested.* at overflow, tcy returns to h'0000 and starts counting up again. during interval timer operation, when a value is set in tly, the same value is set in tcy. note: * for details on interrupts, see 3.3, interrupts. 2. auto-reload timer operation setting bit tmy7 in tmy to 1 causes timer y to function as a 16-bit auto-reload timer. when a reload value is set in tly, the same value is loaded into tcy, becoming the value from which tcy starts its count. after the count value in tcy reaches h'ffff, the next clock signal input causes timer y to overflow. the tly value is then loaded into tcy, and the count continues from that value. the overflow period can be set within a range from 1 to 65536 input clocks, depending on the tly value. the clock sources and interrupts in auto-reload mode are the same as in interval mode. in auto-reload mode, when a new value is set in tly, the tly value is also set in tcy. 3. event counter operation timer y can operate as an event counter, counting rising or falling edges of an event signal input at pin tmiy. external event counting is selected by setting bits tmy2 to tmy0 in timer mode register y to 111. when timer y is used to count external event input, bit inten7 in ienr3 should be cleared to 0 to disable int 7 interrupt requests. 259 9.10.5 timer y operation states table 9-10-3 summarizes the timer y operation states. table 9-10-3 timer y operation states sub- sub- operation mode reset active sleep watch active sleep standby tcy interval reset functions functions halted halted halted halted auto reload reset functions functions halted halted halted halted tmy reset functions retained retained retained retained retained 260 9.11 watchdog timer 9.11.1 overview the watchdog timer has an 8-bit counter that is incremented by an input clock. if a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. 1. features features of the watchdog timer are given below. incremented by internal clock source (?8192). a reset signal is generated when the counter overflows. the overflow period can be set from from 1 to 256 times 8192/?(from approximately 2 ms to 500 ms when ?= 4.19 mhz). 2. block diagram figure 9-11-1 shows a block diagram of the watchdog timer. figure 9-11-1 block diagram of watchdog timer pss tcsrw tcsrw ?8192 notation: tcsrw: tcw: pss: internal data bus reset signal timer control/status register w timer counter w prescaler s 261 3. register configuration table 9-11-1 shows the register configuration of the watchdog timer. table 9-11-1 watchdog timer registers name abbrev. r/w initial value address timer control/status register w tcsrw r/w h'aa h'ffbe timer counter w tcw r/w h'00 h'ffbf 9.11.2 register descriptions 1. timer control/status register w (tcsrw) tcsrw is an 8-bit read/write register that controls write access to tcw and tcsrw itself, controls watchdog timer operations, and indicates operating status. upon reset, tcsrw is initialized to h'aa. bit 7: bit 6 write inhibit (b6wi) bit 7 controls the writing of data to bit 6 in tcsrw. bit 7 b6wi description 0 bit 6 is write-enabled 1 bit 6 is write-protected (initial value) this bit is always read as 1. data written to this bit is not stored. bit initial value read/write 7 b6wi 1 r 6 tcwe 0 r/w 5 b4wi 1 r 4 tcsrwe 0 r/w 3 b2wi 1 r 0 wrst 0 r/w 2 wdon 0 r/w 1 b0wi 1 r * note: * * * * write is permitted only under certain conditions, which are given in the descriptions of the individual bits. 262 bit 6: timer counter w write enable (tcwe) bit 6 controls the writing of data to tcw. bit 6 tcwe description 0 data cannot be written to tcw (initial value) 1 data can be written to tcw bit 5: bit 4 write inhibit (b4wi) bit 5 controls the writing of data to bit 4 in tcsrw. bit 5 b4wi description 0 bit 4 is write-enabled (initial value) 1 bit 4 is write-protected this bit is always read as 1. data written to this bit is not stored. bit 4: timer control/status register w write enable (tcsrwe) bit 4 controls the writing of data to tcsrw bits 2 and 0. bit 4 tcsrwe description 0 data cannot be written to bits 2 and 0 (initial value) 1 data can be written to bits 2 and 0 bit 3: bit 2 write inhibit (b2wi) bit 3 controls the writing of data to bit 2 in tcsrw. bit 3 b2wi description 0 bit 2 is write-enabled 1 bit 2 is write-protected (initial value) this bit is always read as 1. data written to this bit is not stored. 263 bit 2: watchdog timer on (wdon) bit 2 enables watchdog timer operation. bit 2 wdon description 0 watchdog timer operation is disabled (initial value) clearing conditions: reset, or when tcsrwe = 1 and 0 is written in both b2wi and wdon 1 watchdog timer operation is enabled setting conditions: when tcsrwe = 1 and 0 is written in b2wi and 1 is written in wdon counting starts when this bit is set to 1, and stops when this bit is cleared to 0. bit 1: bit 0 write inhibit (b0wi) bit 1 controls the writing of data to bit 0 in tcsrw. bit 1 b0wi description 0 bit 0 is write-enabled 1 bit 0 is write-protected (initial value) this bit is always read as 1. data written to this bit is not stored. bit 0: watchdog timer reset (wrst) bit 0 indicates that tcw has overflowed, generating a reset signal. the reset signal generated by the overflow resets the entire chip. wrst is cleared to 0 by a reset from the res pin, or when software writes 0. bit 0 wrst description 0 clearing conditions: (initial value) reset by res pin when tcsrwe = 1, and 0 is written in both b0wi and wrst 1 setting conditions: when tcw overflows and a reset signal is generated 264 2. timer counter w (tcw) tcw is an 8-bit read/write up-counter, which is incremented by internal clock input. the input clock is ?8192. the tcw value can always be written or read by the cpu. when tcw overflows from h'ff to h'00, an internal reset signal is generated and wrst is set to 1 in tcsrw. upon reset, tcw is initialized to h'00. 9.11.3 timer operation the watchdog timer has an 8-bit counter (tcw) that is incremented by clock input (?8192). when tcsrwe = 1 in tcsrw, if 0 is written in b2wi and 1 is simultaneously written in wdon, tcw starts counting up. when the tcw count value reaches h'ff, the next clock input causes the watchdog timer to overflow and generates an internal reset signal. the internal reset signal is output for 512 clock cycles of the osc clock. it is possible to write to tcw, causing tcw to count up from the written value. the overflow period can be set in the range from 1 to 256 input clocks, depending on the value written in tcw. bit initial value read/write 7 tcw7 0 r/w 6 tcw6 0 r/w 5 tcw5 0 r/w 4 tcw4 0 r/w 3 tcw3 0 r/w 0 tcw0 0 r/w 2 tcw2 0 r/w 1 tcw1 0 r/w 265 figure 9-11-2 shows an example of watchdog timer operations. example: ?= 4 mhz and the desired overflow period is 30 ms. 4 10 6 30 10 ? = 14.6 8192 the value set in tcw should therefore be 256 ?15 = 241 (h'f1). figure 9-11-2 typical watchdog timer operations (example) 9.11.4 watchdog timer operation states table 9-11-2 summarizes the watchdog timer operation states. table 9-11-2 watchdog timer operation states sub- sub- operation mode reset active sleep watch active sleep standby tcw reset functions functions halted halted halted halted tcsrw reset functions functions retained retained retained retained h'f1 tcw overflow start h'f1 written in tcw h'f1 written in tcw reset internal reset signal 512 osc clock cycles h'ff h'00 tcw count value 266 section 10 serial communication interface 10.1 overview the h8/3927 series is provided with a two-channel serial communication interface (sci). table 10-1-1 summarizes the functions and features of the two sci channels. table 10-1-1 serial communication interface functions channel functions features sci1 synchronous serial transfer choice of 8-bit or 16-bit data length continuous clock output sci2 synchronous serial transfer automatic transfer of up to 32 bytes of data (send, receive, or simultaneous send/receive) chip select input strobe pulse output 10.2 sci1 10.2.1 overview serial communication interface 1 (sci1) performs synchronous serial transfer of 8-bit or 16-bit data. 1. features choice of 8-bit or 16-bit data length choice of eight internal clock sources (?1024, ?256, ?64, ?32, ?16, ?8, ?4, ?2) or an external clock interrupt requested at completion of transfer 267 choice of 8 internal clocks (?1024 to ?2) or external clock open drain output possible interrupt requested at completion of transfer choice of 7 internal clocks (?256 to ?2) or external clock open drain output possible interrupt requested at completion of transfer or error 2. block diagram figure 10-2-1 shows a block diagram of sci1. figure 10-2-1 sci1 block diagram h8/3834 '92 fig. 10-2-1 sck 1 si 1 so 1 scr1 scsr1 sdru sdrl pss transfer bit counter transmit/receive control circuit internal data bus notation: scr1: scsr1: sdru: sdrl: irrs1: pss: serial control register 1 serial control/status register 1 serial data register u serial data register l sci1 interrupt request flag prescaler s irrs1 268 3. pin configuration table 10-2-1 shows the sci1 pin configuration. table 10-2-1 pin configuration name abbrev. i/o function sci1 clock pin sck 1 i/o sci1 clock input or output sci1 data input pin si 1 input sci1 receive data input sci1 data output pin so 1 output sci1 transmit data output 4. register configuration table 10-2-2 shows the sci1 register configuration. table 10-2-2 sci1 registers name abbrev. r/w initial value address serial control register 1 scr1 r/w h'00 h'ffa0 serial control status register 1 scsr1 r/w h'80 h'ffa1 serial data register u sdru r/w not fixed h'ffa2 serial data register l sdrl r/w not fixed h'ffa3 10.2.2 register descriptions 1. serial control register 1 (scr1) scr1 is an 8-bit read/write register for selecting the operation mode, the transfer clock source, and the prescaler division ratio. upon reset, scr1 is initialized to h'00. writing to this register during a transfer stops the transfer. h124 '92 h8/3834 u.m. scr1 bit initial value read/write 7 snc1 0 r/w 6 snc0 0 r/w 5 0 r/w 4 0 r/w 3 cks3 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w 269 bits 7 and 6: operation mode select 1, 0 (snc1, snc0) bits 7 and 6 select the operation mode. bit 7 bit 6 snc1 snc0 description 0 0 8-bit synchronous transfer mode (initial value) 0 1 16-bit synchronous transfer mode 1 0 continuous clock output mode * 1 1 1 reserved * 2 notes: 1. pins si 1 and so 1 should be used as general input or output ports. 2. don? set bits snc1 and snc0 to 11. bits 5 and 4: reserved bits bits 5 and 4 are reserved, but they can be written and read. bit 3: clock source select (cks3) bit 3 selects the clock source and sets pin sck 1 as an input or output pin. bit 3 cks3 description 0 clock source is prescaler s, and pin sck 1 is output pin (initial value) 1 clock source is external clock, and pin sck 1 is input pin bits 2 to 0: clock select (cks2 to cks 0) when cks3 = 0, bits 2 to 0 select the prescaler division ratio and the serial clock cycle. bit 2 bit 1 bit 0 serial clock cycle cks2 cks1 cks0 prescaler division ?= 5 mhz ?= 2.5 mhz 0 0 0 ?1024 (initial value) 204.8 s 409.6 s 0 0 1 ?256 51.2 s 102.4 s 0 1 0 ?64 12.8 s 25.6 s 0 1 1 ?32 6.4 s 12.8 s 1 0 0 ?16 3.2 s 6.4 s 1 0 1 ?8 1.6 s 3.2 s 1 1 0 ?4 0.8 s 1.6 s 1 1 1 ?2 0.8 s 270 2. serial control/status register 1 (scsr1) note: * only a write of 0 for flag clearing is possible. scsr1 is an 8-bit read/write register indicating operation status and error status. upon reset, scsr1 is initialized to h'80. bit 7: reserved bit bit 7 is reserved; it is always read as 1, and cannot be modified. bit 6: extended data bit (sol) bit 6 sets the so 1 output level. when read, sol returns the output level at the so 1 pin. after completion of a transmission, so 1 continues to output the value of the last bit of transmitted data. the so 1 output can be changed by writing to sol before or after a transmission. the sol bit setting remains valid only until the start of the next transmission. to control the level of the so 1 pin after transmission ends, it is necessary to write to the sol bit at the end of each transmission. do not write to this register while transmission is in progress, because that may cause a malfunction. bit 6 sol description 0 read: so 1 pin output level is low (initial value) write: so 1 pin output level changes to low 1 read: so 1 pin output level is high write: so 1 pin output level changes to high bit initial value read/write 7 ? 1 6 sol 0 r/w 5 orer 0 r/(w) 4 ? 0 3 ? 0 0 stf 0 r/w 2 ? 0 1 ? 0 * 271 bit 5: overrun error flag (orer) when an external clock is used, bit 5 indicates the occurrence of an overrun error. if a clock pulse is input after transfer completion, this bit is set to 1 indicating an overrun. if noise occurs during a transfer, causing an extraneous pulse to be superimposed on the normal serial clock, incorrect data may be transferred. bit 5 orer description 0 clearing conditions: (initial value) after reading orer = 1, cleared by writing 0 to orer 1 setting conditions: set if a clock pulse is input after transfer is complete, when an external clock is used bits 4 to 2: reserved bits bits 4 to 2 are reserved. they are always read as 0, and cannot be modified. bit 1: reserved bit bit 1 is reserved; it should always be cleared to 0. bit 0: start flag (stf) bit 0 controls the start of a transfer. setting this bit to 1 causes sci1 to start transferring data. during the transfer or while waiting for the first clock pulse, this bit remains set to 1. it is cleared to 0 upon completion of the transfer. it can therefore be used as a busy flag. bit 0 stf description 0 read: indicates that transfer is stopped (initial value) write: invalid 1 read: indicates transfer in progress write: starts a transfer operation 272 3. serial data register u (sdru) sdru is an 8-bit read/write register. it is used as the data register for the upper 8 bits in 16-bit transfer (sdrl is used for the lower 8 bits). data written to sdru is output to sdrl starting from the least significant bit (lsb). this data is then replaced by lsb-first data input at pin si1, which is shifted in the direction from the most significant bit (msb) toward the lsb. sdru must be written or read only after data transmission or reception is complete. if this register is written or read while a data transfer is in progress, the data contents are not guaranteed. the sdru value upon reset is not fixed. 4. serial data register l (sdrl) sdrl is an 8-bit read/write register. it is used as the data register in 8-bit transfer, and as the data register for the lower 8 bits in 16-bit transfer (sdru is used for the upper 8 bits). in 8-bit transfer, data written to sdrl is output from pin so 1 starting from the least significant bit (lsb). this data is than replaced by lsb-first data input at pin si 1 , which is shifted in the direction from the most significant bit (msb) toward the lsb. in 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via sdru. sdrl must be written or read only after data transmission or reception is complete. if this register is read or written while a data transfer is in progress, the data contents are not guaranteed. the sdrl value upon reset is not fixed. h124 '92 h8/3834 u.m. sdrl bit initial value read/write 7 sdrl7 not fixed r/w 6 sdrl6 not fixed r/w 5 sdrl5 not fixed r/w 4 sdrl4 not fixed r/w 3 sdrl3 not fixed r/w 0 sdrl0 not fixed r/w 2 sdrl2 not fixed r/w 1 sdrl1 not fixed r/w h037 '92 h8/3834 u.m. sdru bit initial value read/write 7 sdru7 not fixed r/w 6 sdru6 not fixed r/w 5 sdru5 not fixed r/w 4 sdru4 not fixed r/w 3 sdru3 not fixed r/w 0 sdru0 not fixed r/w 2 sdru2 not fixed r/w 1 sdru1 not fixed r/w 273 10.2.3 operation data can be sent and received in an 8-bit or 16-bit format, synchronized to an internal or external serial clock. overrun errors can be detected when an external clock is used. 1. clock the serial clock can be selected from a choice of eight internal clocks and an external clock. when an internal clock source is selected, pin sck 1 becomes the clock output pin. when continuous clock output mode is selected (scr1 bits snc1 and snc0 are set to 10), the clock signal (?1024 to ?2) selected in bits cks2 to cks0 is output continuously from pin sck 1 . when an external clock is used, pin sck 1 is the clock input pin. 2. data transfer format figure 10-2-2 shows the data transfer format. data is sent and received starting from the least significant bit, in lsb-first format. transmit data is output from one falling edge of the serial clock until the next falling edge. receive data is latched at the rising edge of the serial clock. figure 10-2-2 transfer format 3. data transfer operations transmitting a transmit operation is carried out as follows. 1. set bits so1 and sck1 to 1 in pmr3 to select the so 1 and sck 1 pin functions. if necessary, set bit pof1 in pmr7 for nmos open-drain output at pin so 1 . 2. clear bit snc1 in scr1 to 0, and set bit snc0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. select the serial clock in bits cks3 to cks0. writing data to scr1 initializes the internal state of sci1. 3. write transmit data in sdrl and sdru, as follows. 8-bit transfer mode: sdrl 16-bit transfer mode: upper byte in sdru, lower byte in sdrl h037 '92 h8/3834 u.m. fig. 10-2-2 sck so /si 1 1 1 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 274 4. set the scsr1 start flag (stf) to 1. sci1 starts operating and outputs transmit data at pin so 1 . 5. after data transmission is complete, bit irrs1 in interrupt request register 2 (irr2) is set to 1. when an internal clock is used, a serial clock is output from pin sck 1 in synchronization with the transmit data. after data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. during this time, pin so 1 continues to output the value of the last bit transmitted. when an external clock is used, data is transmitted in synchronization with the serial clock input at pin sck 1 . after data transmission is complete, an overrun occurs if the serial clock continues to be input; no data is transmitted and the scsr1 overrun error flag (bit orer) is set to 1. while transmission is stopped, the output value of pin so 1 can be changed by rewriting bit sol in scsr1. receiving a receive operation is carried out as follows. 1. set bits si1 and sck1 to 1 in pmr3 to select the si 1 and sck 1 pin functions. 2. clear bit snc1 in scr1 to 0, and set bit snc0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. select the serial clock in bits cks3 to cks0. writing data to scr1 initializes the internal state of sci1. 3. set the scsr1 start flag (stf) to 1. sci1 starts operating and receives data at pin si 1 . 4. after data reception is complete, bit irrs1 in interrupt request register 2 (irr2) is set to 1. 5. read the received data from sdrl and sdru, as follows. 8-bit transfer mode: sdrl 16-bit transfer mode: upper byte in sdru, lower byte in sdrl 6. after data reception is complete, an overrun occurs if the serial clock continues to be input; no data is received and the scsr1 overrun error flag (bit orer) is set to 1. 275 simultaneous transmit/receive a simultaneous transmit/receive operation is carried out as follows. 1. set bits so1, si1, and sck1 to 1 in pmr3 to select the so 1 , si 1 , and sck 1 pin functions. if necessary, set bit pof1 in pmr7 for nmos open-drain output at pin so 1 . 2. clear bit snc1 in scr1 to 0, and set bit snc0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. select the serial clock in bits cks3 to cks0. writing data to scr1 initializes the internal state of sci1. 3. write transmit data in sdrl and sdru, as follows. 8-bit transfer mode: sdrl 16-bit transfer mode: upper byte in sdru, lower byte in sdrl 4. set the scsr1 start flag (stf) to 1. sci1 starts operating. transmit data is output at pin so 1 . receive data is input at pin si 1 . 5. after data transmission and reception are complete, bit irrs1 in irr2 is set to 1. 6. read the received data from sdrl and sdru, as follows. 8-bit transfer mode: sdrl 16-bit transfer mode: upper byte in sdru, lower byte in sdrl when an internal clock is used, a serial clock is output from pin sck 1 in synchronization with the transmit data. after data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. during this time, pin so 1 continues to output the value of the last bit transmitted. when an external clock is used, data is transmitted and received in synchronization with the serial clock input at pin sck 1 . after data transmission and reception are complete, an overrun occurs if the serial clock continues to be input; no data is transmitted or received and the scsr1 overrun error flag (bit orer) is set to 1. while transmission is stopped, the output value of pin so 1 can be changed by rewriting bit sol in scsr1. 276 10.2.4 interrupts sci1 can generate an interrupt at the end of a data transfer. when an sci1 transfer is complete, bit irrs1 in interrupt request register 2 (irr2) is set to 1. sci1 interrupt requests can be enabled or disabled by bit iens1 of interrupt enable register 2 (ienr2). for further details, see 3.3, interrupts. 277 10.3 sci2 10.3.1 overview serial communication interface 2 (sci2) has a 32-bit data buffer for synchronous serial transfer of up to 32 bytes of data in one operation. 1. features features of sci are listed below. automatic transfer of up to 32 bytes of data choice of seven internal clock sources (?256, ?64, ?32, ?16, ?8, ?4, ?2) or an external clock interrupts requested at completion of transfer or when an error occurs gaps of 56, 24, or 8 internal clock cycles can be inserted between successive bytes of transferred data. transfer can be started by chip select input. a strobe pulse can be output for each byte transferred. 278 2. block diagram figure 10-3-1 shows a block diagram of sci2. figure 10-3-1 sci2 block diagram sck strb cs so si pss star edar scr2 scsr2 transmit/receive control circuit shift register serial data buffer internal data bus notation: star: edar: scr2: scsr2: irrs2: pss: start address register end address register serial control register 2 serial control/status register 2 serial communication interface 2 interrupt request flag (interrupt request register 2) prescaler s irrs2 2 2 2 279 3. pin configuration table 10-3-1 shows the sci2 pin configuration. table 10-3-1 pin configuration name abbrev. i/o function sci2 clock pin sck 2 i/o sci2 clock input/output sci2 data input pin si 2 input sci2 receive data input sci2 data output pin so 2 output sci2 transmit data output sci2 strobe pin strb output sci2 strobe signal output sci2 chip select pin cs input sci2 chip select input 4. register configuration table 10-3-2 shows the sci2 register configuration. table 10-3-2 sci2 registers name abbrev. r/w initial value address start address register star r/w h'e0 h'ffa4 end address register edar r/w h'e0 h'ffa5 serial control register 2 scr2 r/w h'e0 h'ffa6 serial control/status register 2 scsr2 r/w h'e0 h'ffa7 serial data buffer (32 bytes) r/w not fixed h'ff80 to h'ff9f 10.3.2 register descriptions 1. start address register (star) star is an 8-bit read/write register, for designating a transfer start address in the address space (h'ff80 to h'ff9f) allocated to the 32-byte data buffer. the lower 5 bits of star correspond to the lower 5 bits of the address. the extent of continuous data transfer is defined in star and in the end address register (edar). if the same value is designated by star and edar, only 1 byte of data is transferred. bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. upon reset, star is initialized to h'e0. h037 '92 h8/3834 u.m. star bit initial value read/write 7 1 6 1 5 1 4 sta4 0 r/w 3 sta3 0 r/w 0 sta0 0 r/w 2 sta2 0 r/w 1 sta1 0 r/w 280 2. end address register (edar) edar is an 8-bit read/write register, for designating a transfer end address in the address space (h'ff80 to h'ff9f) allocated to the 32-byte data buffer. the lower 5 bits of edar correspond to the lower 5 bits of the address. the extent of continuous data transfer is defined in star and in edar. if the same value is designated by star and edar, only 1 byte of data is transferred. bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. upon reset, edar is initialized to h'e0. 3. serial control register 2 (scr2) scr2 is an 8-bit read/write register for selecting the serial clock, and for setting the gap inserted between data during continuous transfer when sci2 uses an internal clock. upon reset, scr2 is initialized to h'e0. bits 7 to 5: reserved bits bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. bits 4 and 3: gap select (gap1 to gap0) when sci2 uses an internal clock, gaps can be inserted between successive data bytes. bits 4 and 3 designate the length of these gaps. during a gap, pin sck 2 remains at the high level. when no gap is inserted, the strb signal stays at the low level. bit 4 bit 3 gap1 gap0 description 0 0 no gaps between bytes (initial value) 0 1 a gap of 8 clock cycles is inserted between bytes 1 0 a gap of 24 clock cycles is inserted between bytes 1 1 a gap of 56 clock cycles is inserted between bytes h037 '92 h8/3834 u.m. scr2 bit initial value read/write 7 1 6 1 5 1 4 gap1 0 r/w 3 gap0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w h037 '92 h8/3834 u.m. edar bit initial value read/write 7 1 6 1 5 1 4 eda4 0 r/w 3 eda3 0 r/w 0 eda0 0 r/w 2 eda2 0 r/w 1 eda1 0 r/w 281 bits 2 to 0: clock select (cks2 to cks0) bits 2 to 0 select one of seven internal clock sources or an external clock. bit 2 bit 1 bit 0 clock serial clock cycle cks2 cks1 cks0 pin sck 2 source prescaler division ?= 5 mhz ? 2.5 mhz 0 0 0 sck 2 output prescaler s ?256 (initial value) 51.2 s 102.4 s 0 0 1 ?64 12.8 s 25.6 s 0 1 0 ?32 6.4 s 12.8 s 0 1 1 ?16 3.2 s 6.4 s 1 0 0 ?8 1.6 s 3.2 s 1 0 1 ?4 0.8 s 1.6 s 1 1 0 ?2 0.8 s 1 1 1 sck 2 input external clock 4. serial control/status register 2 (scsr2) note: * only a write of 0 for flag clearing is possible. scsr2 is an 8-bit register indicating sci2 operation status and error status. upon reset, scsr2 is initialized to h'e0. bits 7 to 5: reserved bits bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. h124 '92 h8/3834 u.m. scsr2 bit initial value read/write 7 1 6 1 5 1 4 sol 0 r/w 3 orer 0 r/(w) 0 stf 0 r/w 2 wt 0 r/(w) 1 abt 0 r/(w) * * * 282 bit 4: extended data bit (sol) bit 4 sets the so 2 output level. when read, sol returns the output level at the so 2 pin. after completion of a transmission, so 2 continues to output the value of the last bit of transmitted data. the so 2 output can be changed by writing to sol before or after a transmission. the sol bit setting remains valid only until the start of the next transmission. to control the level of the so 2 pin after transmission ends, it is necessary to write to the sol bit at the end of each transmission. do not write to this register while transmission is in progress, because that may cause a malfunction. bit 4 sol description 0 read: so 2 pin output level is low (initial value) write: so 2 pin output level changes to low 1 read: so 2 pin output level is high write: so 2 pin output level changes to high bit 3: overrun error flag (orer) when an external clock is used, bit 3 indicates the occurrence of an overrun error. if a clock pulse is input after transfer completion, this bit is set to 1 indicating an overrun. if noise occurs during a transfer, causing an extraneous pulse to be superimposed on the normal serial clock, incorrect data may be transferred. overrun errors are not detected while pin cs is at the high level. bit 3 orer description 0 clearing conditions: (initial value) after reading orer = 1, cleared by writing 0 to orer 1 setting conditions: set if a clock pulse is input after transfer is complete, when an external clock is used bit 2: wait flag (wt) bit 2 indicates that an attempt was made to read or write the 32-byte serial data buffer while a transfer was in progress, or while waiting for cs input. the read or write access is not carried out, and this bit is set to 1. bit 2 wt description 0 clearing conditions: (initial value) after reading wt = 1, cleared by writing 0 to wt 1 setting conditions: an attempt was made to read or write the (32-byte) serial data buffer during a transfer operation or while waiting for cs input 283 bit 1: abort flag (abt) bit 1 indicates that cs went to high during data transfer. when the cs input function is selected, if a high-level signal is detected at pin cs during a transfer, the transfer is immediately aborted and this bit is set to 1. at the same time bit irrs2 in interrupt request register 2 (irr2) is set to 1, and pins sck 2 and so 2 go to the high-impedance state. data in the (32-byte) serial data buffer and values in the internal registers other than scsr2 remain unchanged. transfer cannot take place while this bit is set to 1. it must be cleared to 0 before resuming the transfer. bit 1 abt description 0 clearing conditions: (initial value) after reading abt = 1, cleared by writing 0 to abt 1 setting conditions: when pin cs goes high during a transfer bit 0: start/busy flag (stf) bit 0 controls the start of a transfer. if bit cs = 0 in pmr3, setting bit stf to 1 causes sci2 to start transferring data. if bit cs = 1 in pmr3, then after stf is set to 1, sci2 starts transferring data when cs goes low. this bit stays at 1 during the transfer or while waiting for cs input; it is cleared to 0 after the transfer is completed or when the transfer is aborted by cs . it can therefore be used as a busy flag. clearing this bit to 0 during a transfer aborts the transfer, initializing sci2. the contents of the (32-byte) serial data buffer and of internal registers other than scsr2 remain unchanged. bit 0 stf description 0 read: indicates that transfer is stopped (initial value) write: stops a transfer operation 1 read: indicates transfer in progress or waiting for cs input write: starts a transfer operation 284 10.3.3 operation sci2 has a 32-byte serial data buffer, making possible continuous transfer of up to 32 bytes of data with one operation. sci2 transmits and receives data in synchronization with clock pulses. depending on register settings, it can transmit, receive, or transmit and receive simultaneously. when it transmits but does not receive, the serial data buffer values are retained after the transmission is completed. either an internal clock or external clock may be selected as the serial clock. when an internal clock is selected, gaps may be inserted between the data bytes. it is also possible to output a strobe signal at pin strb. when an external clock is selected, the overrun flag allows detection of erroneous operation due to unwanted clock input. transfers can be started or aborted by input at pin cs . abort is indicated by means of an abort flag. 1. clock the serial clock can be selected from a choice of six internal clock sources or an external clock. when an internal clock source is selected, pin sck 2 becomes the clock output pin. 2. data transfer format figure 10-3-2 and figure 10-3-3 show the sci2 data transfer format. data is sent and received starting from the least significant bit, in lsb-first format. transmit data is output from one falling edge of the serial clock until the next falling edge. receive data is latched at the rising edge of the serial clock. when sci2 operates on an internal clock, a gap can be inserted between each byte of transferred data and the next, as shown in figure 10-3-3. during this gap, pin sck 2 outputs a high-level signal. also, a strobe pulse can be output at pin strb. the length of the gap is designated in bits gap1 and gap0 in serial control register 2 (scr2). 285 figure 10-3-2 data transfer format (no gaps between data) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 transfer started transfer completed sck so /si cs strb 2 2 2 h8/3834 u.m. '92 fig. 10-3-2 286 figure 10-3-3 data transfer format (gap inserted between data) bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 sck so /si cs strb 2 2 2 transfer started transfer completed 8, 24, or 56 clock cycles h8/3834 u.m. '92 fig. 10-3-3 287 3. data transfer operations sci2 initialization data transfer on sci2 first of all requires that sci2 be initialized by software as follows. 1. with bit stf cleared to 0 in scsr2, select pin functions and the transfer mode in registers pmr7, pmr3, star, edar, and scr2. 2. the sci2 pins double as general input/output ports. switching between port and sci2 functions is controlled in pmr3. cmos output or nmos open drain output can be selected in pmr7. the serial clock and gaps between transferred bytes are set in scr2. 3. the start and end addresses of the transfer data area are set in star and edar. if the end address is set smaller than the start address, as shown in figure 10-3-4, the transfer wraps around from h'ff9f to h'ff80 and continues to the end address. if the start address and end address are the same, only one byte of data will be transferred. figure 10-3-4 operation when end address is smaller than start address h'ff80 h'ff9f end address start address end start h037 '92 h8/3834 fig. 10-3-4 288 transmitting a transmit operation is carried out as follows. 1. set bits so2 and sck2 to 1 in pmr3 to select the so 2 and sck 2 pin functions. if necessary, set bit pof2 in pmr7 for nmos open-drain output at pin so 2 , and set bits cs and strb in pmr3 to select the cs and strb pin functions. 2. select the serial clock and, in the case of internal clock operation, the data gap in scr2. 3. write transmit data in the serial data buffer. this data will remain in the data buffer after completion of the transfer. it is not necessary to rewrite the buffer when the same data is retransmitted. 4. set the start address in the lower 5 bits of star, and the end address in the lower 5 bits of edar. 5. set the start/busy flag (stf) to 1. if bit cs = 0 in pmr3, transmission starts as soon as stf is set to 1. if cs = 1 in pmr3, transmission starts when cs goes low. 6. after data transmission is complete, bit irrs2 in interrupt request register 2 (irr2) is set to 1, and bit stf is cleared to 0. when an internal clock is used, a serial clock is output from pin sck 2 in synchronization with the transmit data. after data transmission is completed, the serial clock is not output until bit stf is set again. during this time, pin so 2 continues to output the value of the last bit transmitted. when an external clock is used, data is transmitted in synchronization with the serial clock input at pin sck 2 . after data transmission is completed, an overrun occurs if the serial clock continues to be input; no data is transmitted and the scsr2 overrun error flag (bit orer) is set to 1. pin so 2 continues to output the value of the last preceding bit. overrun errors are not detected when both pin cs is at the high level and pmr3 bit cs = 1. while transmission is stopped, the output value of pin so 2 can be changed by rewriting bit sol in scsr2. during a transmission or while waiting for cs input, the cpu cannot read or write the data buffer. if a read instruction is executed, h'ff will be read; if a write instruction is executed, the buffer contents will not change. in either case the wait flag (bit wt) in scsr2 will be set to 1. if bit cs = 1 in pmr3 and during transmission a high-level signal is detected at pin cs , the transmit operation will immediately be aborted, setting the abort flag (bit abt) to 1. at the same time bit irrs2 in interrupt request register 2 (irr2) will be set to 1, and bit stf will be cleared to 0. pins sck 2 and so 2 will go to the high-impedance state. data transfer is not possible while bit abt is set to 1. it must be cleared before resuming the transfer. 289 receiving a receive operation is carried out as follows. 1. set bits si2 and sck2 in port mode register 3 (pmr3) to 1, designating use of the si 2 and sck 2 pin functions. if necessary, set bit cs in pmr3 to select the cs pin function. 2. select the serial clock and, in the case of internal clock operation, the data gap in scr2. 3. allocate an area to hold the received data in the serial data buffer by designating the receive start address in the lower 5 bits of the start address register (star) and the receive end address in the lower 5 bits of the end address register (edar). 4. set the start/busy flag (bit stf) to 1. if bit cs = 0 in pmr3, receiving starts as soon as stf is set. if cs = 1 in pmr3, receiving starts when cs goes low. 5. after receiving is completed, bit irrs2 in interrupt request register 2 (irr2) is set to 1, and bit stf is cleared to 0. 6. read the received data from the serial data buffer. if an internal clock is used, a serial clock is output from pin sck 2 when the receive operation starts. after receiving is completed, the serial clock is not output until bit stf is set again. when an external clock source is used, data is received in synchronization with the clock input at pin sck 2 . after receiving is completed, an overrun occurs if the serial clock continues to be input; no further data is received and the scsr2 overrun error flag (bit orer) is set to 1. overrun errors are not detected when both pin cs is high and bit cs = 1 in pmr3. while receiving or while waiting for cs input, the cpu cannot read or write the data buffer. if a read instruction is executed, h'ff will be read; if a write instruction is executed the buffer contents will not change. in either case the wait flag (bit wt) in scsr2 will be set to 1. if bit cs = 1 in pmr3 and a high-level signal is detected at pin cs during receiving, the receive operation will immediately be aborted, setting the abort flag (bit abt) to 1. at the same time bit irrs2 in interrupt request register 2 (irr2) will be set to 1, and bit stf will be cleared to 0. pins sck 2 and so 2 will go to the high-impedance state. data transfer is not possible while bit abt is set to 1. it must be cleared before resuming the transfer. 290 simultaneous transmit/receive a simultaneous transmit/receive operation is carried out as follows. 1. set bits so2, si2, and sck2 in pmr3 to 1, designating use of the so 2 , si 2 , and sck 2 pin functions. if necessary, set bit pof2 in port mode register 7 (pmr7) for nmos open-drain output at pin so 2 , and set bits cs and strb to designate use of the cs and strb pin functions. 2. select the serial clock and, in the case of internal clock operation, the data gap in scr2. 3. write transmit data in the serial data buffer. in simultaneous transmit/receive, received data replaces transmitted data at the same buffer addresses. 4. set the transfer start address in the lower 5 bits of star, and the transfer end address in the lower 5 bits of edar. 5. set the start/busy flag (bit stf) to 1. if bit cs = 0 in pmr3, the transmit/receive transfer starts as soon as stf is set to 1. if cs = 1 in pmr3, transfer operations start when cs goes low. 6. after data transfer is completed, bit irrs2 in interrupt request register 2 (irr2) is set to 1, and bit stf is cleared to 0. 7. read the received data from the serial data buffer. if an internal clock is used, a serial clock is output from pin sck 2 when the transfer begins. after the transfer is completed, the serial clock is not output until bit stf is set again. during this time, pin so 2 continues to output the value of the last bit transmitted. when an external clock is used, data is transferred in synchronization with the serial clock input at pin sck 2 . after the transfer is completed, an overrun occurs if the serial clock continues to be input; no transfer operation takes place and the scsr2 overrun error flag (bit orer) is set to 1. pin so 2 continues to output the value of the last transmitted bit. overrun errors are not detected when both pin cs is high and bit cs = 1 in pmr3. while data transfer is stopped, the output value of pin so 2 can be changed by rewriting bit sol in scsr2. during a transfer or while waiting for cs input, the cpu cannot read or write the data buffer. if a read instruction is executed, h'ff will be read; if a write instruction is executed the buffer contents will not change. in either case the wait flag (bit wt) in scsr2 will be set to 1. if bit cs = 1 in pmr3 and during the transfer a high-level signal is detected at pin cs , the transfer will immediately be aborted, setting the abort flag (bit abt) to 1. at the same time bit irrs2 in interrupt request register 2 (irr2) will be set to 1, and bit stf will be cleared to 0. pins sck 2 and so 2 will go to the high-impedance state. data transfer is not possible while bit abt is set to 1. it must be cleared before resuming the transfer. 291 10.3.4 interrupts sci2 can generate interrupts when a transfer is completed or when a transfer is aborted by cs . these interrupts have the same vector address. when the above conditions occur, bit irrs2 in interrupt request register 2 (irr2) is set to 1. sci2 interrupt requests can be enabled or disabled in bit iens2 of interrupt enable register 2 (ienr2). for further details, see 3.3, interrupts. when a transfer is aborted by cs , an overrun error occurs, or a read or write of the serial data buffer is attempted during a transfer or while waiting for cs input, the abt, orer, or wt bit in scsr2 is set to 1. these bits can be used to determine the cause of the error. 292 section 11 14-bit pwm 11.1 overview the h8/3927 series is provided with a 14-bit pwm (pulse width modulator) on-chip, which can be used as a d/a converter by connecting a low-pass filter. 11.1.1 features features of the 14-bit pwm are as follows. choice of two conversion periods a conversion period of 32,768/? with a minimum modulation width of 2/?or a conversion period of 16,384/? with a minimum modulation width of 1/?can be chosen. pulse division method for less ripple 11.1.2 block diagram figure 11-1 shows a block diagram of the 14-bit pwm. figure 11-1 block diagram of the 14 bit pwm internal data bus pwdrl pwdru pwcr pwm waveform generator ?2 ?4 h8/3834 u.m. '92 fig. 11-1 notation: pwdrl: pwdru: pwcr: pwm data register l pwm data register u pwm control register pwm 293 11.1.3 pin configuration table 11-1 shows the output pin assigned to the 14-bit pwm. table 11-1 pin configuration name abbrev. i/o function pwm output pin pwm output pulse-division pwm waveform output 11.1.4 register configuration table 11-2 shows the register configuration of the 14-bit pwm. table 11-2 register configuration name abbrev. r/w initial value address pwm control register pwcr w h'fe h'ffd0 pwm data register u pwdru w h'c0 h'ffd1 pwm data register l pwdrl w h'00 h'ffd2 294 11.2 register descriptions 11.2.1 pwm control register (pwcr) pwcr is an 8-bit write-only register for input clock selection. upon reset, pwcr is initialized to h'fe. bits 7 to 1: reserved bits bits 7 to 1 are reserved; they are always read as 1, and cannot be modified. bit 0: clock select 0 (pwcr0) bit 0 selects the clock supplied to the 14-bit pwm. this bit is a write-only bit; it is always read as 1. bit 0 pwcr0 description 0 the input clock is ?2 (t = 2/?. the conversion period is 16,384/? (initial value) with a minimum modulation width of 1/? 1 the input clock is ?4 (t = 4/?. the conversion period is 32,768/? with a minimum modulation width of 2/? notation: t : period of pwm input clock h8/3834 u.m. '92 pwcr bit initial value read/write 7 1 6 1 5 1 4 1 3 1 0 pwcr0 0 w 2 1 1 1 295 11.2.2 pwm data registers u and l (pwdru, pwdrl) pwdru and pwdrl form a 14-bit write-only register, with the upper 6 bits assigned to pwdru and the lower 8 bits to pwdrl. the value written to pwdru and pwdrl gives the total high- level width of one pwm waveform cycle. when 14-bit data is written to pwdru and pwdrl, the register contents are latched in the pwm waveform generator, updating the pwm waveform generation data. the 14-bit data should always be written in the following sequence: 1. write the lower 8 bits to pwdrl. 2. write the upper 6 bits to pwdru. pwdru and pwdrl are write-only registers. if they are read, all bits are read as 1. upon reset, pwdru and pwdrl are initialized to h'c000. h8/3834 u.m. '92 pwdru, pwdrl bit initial value read/write 7 1 6 1 5 pwdru5 0 w 4 pwdru4 0 w 3 pwdru3 0 w 0 pwdru0 0 w 2 pwdru2 0 w 1 pwdru1 0 w pwdru bit initial value read/write 7 pwdrl7 0 w 6 pwdrl6 0 w 5 pwdrl5 0 w 4 pwdrl4 0 w 3 pwdrl3 0 w 0 pwdrl0 0 w 2 pwdrl2 0 w 1 pwdrl1 0 w pwdrl 296 11.3 operation when using the 14-bit pwm, set the registers in the following sequence. 1. set bit pwm in port mode register 1 (pmr1) to 1 so that pin p1 4 /pwm is designated for pwm output. 2. set bit pwcr0 in the pwm control register (pwcr) to select a conversion period of either 32,768/?(pwcr0 = 1) or 16,384/?(pwcr0 = 0). 3. set the output waveform data in pwm data registers u and l (pwdru/l). be sure to write in the correct sequence, first pwdrl then pwdru. when data is written to pwdru, the data in these registers will be latched in the pwm waveform generator, updating the pwm waveform generation in synchronization with internal signals. one conversion period consists of 64 pulses, as shown in figure 11-2. the total of the high- level pulse widths during this period (t h ) corresponds to the data in pwdru and pwdrl. this relation can be represented as follows. t h = (data value in pwdru and pwdrl + 64) t /2 where t is the pwm input clock period, either 2/?(bit pwcr0 = 0) or 4/?(bit pwcr0 = 1). example: settings in order to obtain a conversion period of 8,192 s: when bit pwcr0 = 0, the conversion period is 16,384/? so ?must be 2 mhz. in this case t fn = 128 s, with 1/?(resolution) = 0.5 s. when bit pwcr0 = 1, the conversion period is 32,768/? so ?must be 4 mhz. in this case t fn = 128 s, with 2/?(resolution) = 0.5 s. accordingly, for a conversion period of 8,192 s, the system clock frequency (? must be 2 mhz or 4 mhz. 297 figure 11-2 pwm output waveform 1 conversion period t f1 t f2 t f63 t f64 t h1 t h2 t h3 t h63 t h64 t = t + t + t + t = t = t h h1 h2 h3 h64 ..... t f1 f2 f3 h8/3834 u.m. '92 fig. 11-2 ..... = t f84 298 section 12 a/d converter 12.1 overview the h8/3927 series includes on-chip a resistance-ladder-based successive-approximation analog-to- digital converter, and can convert up to 8 channels of analog input. 12.1.1 features the a/d converter has the following features. 8-bit resolution eight input channels conversion time: approx. 12.4 s per channel (at 5 mhz operation) built-in sample-and-hold function interrupt requested on completion of a/d conversion a/d conversion can be started by external trigger input 12.1.2 block diagram figure 12-1 shows a block diagram of the a/d converter. figure 12-1 block diagram of the a/d converter internal data bus amr adsr adrr control logic + com- parator an an an an an an an an adtrg av av cc ss multiplexer reference voltage irrad av cc av ss 0 1 2 3 4 5 6 7 notation: amr: adsr: adrr: a/d mode register a/d start register a/d result register 299 12.1.3 pin configuration table 12-1 shows the a/d converter pin configuration. table 12-1 pin configuration name abbrev. i/o function analog power supply av cc input power supply and reference voltage of analog part analog ground av ss input ground and reference voltage of analog part analog input 0 an 0 input analog input channel 0 analog input 1 an 1 input analog input channel 1 analog input 2 an 2 input analog input channel 2 analog input 3 an 3 input analog input channel 3 analog input 4 an 4 input analog input channel 4 analog input 5 an 5 input analog input channel 5 analog input 6 an 6 input analog input channel 6 analog input 7 an 7 input analog input channel 7 external trigger input adtrg input external trigger input for starting a/d conversion 12.1.4 register configuration table 12-2 shows the a/d converter register configuration. table 12-2 register configuration name abbrev. r/w initial value address a/d mode register amr r/w h'30 h'ffc4 a/d start register adsr r/w h'7f h'ffc6 a/d result register adrr r not fixed h'ffc5 300 12.2 register descriptions 12.2.1 a/d result register (adrr) the a/d result register (adrr) is an 8-bit read-only register for holding the results of analog-to- digital conversion. adrr can be read by the cpu at any time, but the adrr values during a/d conversion are not fixed. after a/d conversion is complete, the conversion result is stored in adrr as 8-bit data; this data is held in adrr until the next conversion operation starts. adrr is not cleared on reset. 12.2.2 a/d mode register (amr) amr is an 8-bit read/write register for specifying the a/d conversion speed, external trigger option, and the analog input pins. upon reset, amr is initialized to h'30. bit 7: clock select (cks) bit 7 sets the a/d conversion speed. bit 7 conversion time cks conversion period ?= 2 mhz ?= 5 mhz 0 62/?(initial value) 31 s 12.4 s 1 31/ 15.5 s * note: * operation is not guaranteed if the conversion time is less than 12.4 s. set bit 7 for a value of at least 12.4 s. h8/3834 u.m. '92 amr bit initial value read/write 7 cks 0 r/w 6 trge 0 r/w 5 1 4 1 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w bit initial value read/write 7 adr7 not fixed r 6 adr6 not fixed r 5 adr5 not fixed r 4 adr4 not fixed r 3 adr3 not fixed r 0 adr0 not fixed r 2 adr2 not fixed r 1 adr1 not fixed r 301 bit 6: external trigger select (trge) bit 6 enables or disables the start of a/d conversion by external trigger input. bit 6 trge description 0 disables start of a/d conversion by external trigger (initial value) 1 enables start of a/d conversion by rising or falling edge of external trigger at pin adtrg * note: * the external trigger ( adtrg ) edge is selected by bit integ5 of iegr2. see 3.3.2 for details. bits 5 and 4: reserved bits bits 5 and 4 are reserved; they are always read as 1, and cannot be modified. bits 3 to 0: channel select (ch3 to ch0) bits 3 to 0 select the analog input channel. the channel selection should be made while bit adsf is cleared to 0. bit 3 bit 2 bit 1 bit 0 ch3 ch2 ch1 ch0 analog input channel 0 0 * * no channel selected (initial value) 0 1 0 0 an 0 0 1 0 1 an 1 0 1 1 0 an 2 0 1 1 1 an 3 1 0 0 0 an 4 1 0 0 1 an 5 1 0 1 0 an 6 1 0 1 1 an 7 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved note: * don? care 302 12.2.3 a/d start register (adsr) the a/d start register (adsr) is an 8-bit read/write register for starting and stopping a/d conversion. a/d conversion is started by writing 1 to the a/d start flag (adsf) or by input of the designated edge of the external trigger signal, which also sets adsf to 1. when conversion is complete, the converted data is set in the a/d result register (adrr), and at the same time adsf is cleared to 0. bit 7: a/d start flag (adsf) bit 7 controls and indicates the start and end of a/d conversion. bit 7 adsf description 0 read: indicates the completion of a/d conversion (initial value) write: stops a/d conversion 1 read: indicates a/d conversion in progress write: starts a/d conversion bits 6 to 0: reserved bits bits 6 to 0 are reserved; they are always read as 1, and cannot be modified. h8/3834 u.m. '92 adsr bit initial value read/write 7 adsf 0 r/w 6 1 5 1 4 1 3 1 0 1 2 1 1 1 303 12.3 operation 12.3.1 a/d conversion operation the a/d converter operates by successive approximations, and yields its conversion result as 8-bit data. a/d conversion begins when software sets the a/d start flag (bit adsf) to 1. bit adsf keeps a value of 1 during a/d conversion, and is cleared to 0 automatically when conversion is complete. the completion of conversion also sets bit irrad in interrupt request register 2 (irr2) to 1. an a/d conversion end interrupt is requested if bit ienad in interrupt enable register 2 (ienr2) is set to 1. if the conversion time or input channel needs to be changed in the a/d mode register (amr) during a/d conversion, bit adsf should first be cleared to 0, stopping the conversion operation, in order to avoid malfunction. 12.3.2 start of a/d conversion by external trigger input the a/d converter can be made to start a/d conversion by input of an external trigger signal. external trigger input is enabled at pin adtrg when bit trge in amr is set to 1. then when the input signal edge designated in bit integ5 of interrupt edge select register 2 (iegr2) is detected at pin adtrg , bit adsf in adsr will be set to 1, starting a/d conversion. figure 12-2 shows the timing. figure 12-2 external trigger input timing pin adtrg (when bit integ5 = 0) adsf a/d conversion h8/3834 u.m. '92 fig. 12-2 304 12.4 interrupts when a/d conversion ends (adsf changes from 1 to 0), bit irrad in interrupt request register 2 (irr2) is set to 1. a/d conversion end interrupts can be enabled or disabled by means of bit ienad in interrupt enable register 2 (ienr2). for further details see 3.3, interrupts. 12.5 typical use an example of how the a/d converter can be used is given below, using channel 1 (pin an1) as the analog input channel. figure 12-3 shows the operation timing. 1. bits ch3 to ch0 of the a/d mode register (amr) are set to 0101, making pin an1 the analog input channel. a/d interrupts are enabled by setting bit ienad to 1, and a/d conversion is started by setting bit adsf to 1. 2. when a/d conversion is complete, bit irrad is set to 1, and the a/d conversion result is stored in the a/d result register (adrr). at the same time adsf is cleared to 0, and the a/d converter goes to the idle state. 3. bit ienad = 1, so an a/d conversion end interrupt is requested. 4. the a/d interrupt handling routine starts. 5. the a/d conversion result is read and processed. 6. the a/d interrupt handling routine ends. if adsf is set to 1 again afterward, a/d conversion starts and steps 2 through 6 take place. figures 12-4 and 12-5 show flow charts of procedures for using the a/d converter. 305 figure 12-3 typical a/d converter operation timing idle a/d conversion (1) idle a/d conversion (2) idle interrupt (irrad) ienad adsf channel 1 (an ) operation state adrr 1 set * set * set * read conversion result read conversion result a/d conversion result (1) a/d conversion result (2) a/d conversion starts note: ( ) indicates instruction execution by software. * conversion result is reset when next conversion starts 306 figure 12-4 flow chart of procedure for using a/d converter (1) (polling by software) start set a/d conversion speed and input channel perform a/d conversion? end yes no disable a/d conversion end interrupt start a/d conversion adsf = 0? no yes read adsr read adrr data h8/3834 u.m. '92 fig. 12-4 307 figure 12-5 flow chart of procedure for using a/d converter (2) (interrupts used) 12.6 application notes data in the a/d result register (adrr) should be read only when the a/d start flag (adsf) in the a/d start register (adsr) is cleared to 0. changing the digital input signal at an adjacent pin during a/d conversion may adversely affect conversion accuracy. start set a/d conversion speed and input channels enable a/d conversion end interrupt start a/d conversion a/d conversion end interrupt? yes no h8/3834 u.m. '92 fig. 12-5 end yes no clear bit irrad to 0 in irr2 read adrr data perform a/d conversion? 308 section 13 d/a converter 13.1 overview the h8/3927 series has on-chip a d/a converter that can output analog voltages on up to four channels. the d/a converter operates by voltage addition, using an r-2r resistor ladder. 13.1.1 features features of the d/a converter are given below. 8-bit resolution four output channels 309 13.1.2 block diagram figure 13-1 shows a block diagram of the d/a converter. figure 13-1 block diagram of d/a converter av cc av ss da 3 da 2 da 1 da 0 internal data bus control logic r-2r circuit r-2r circuit r-2r circuit r-2r circuit dacr0 dadr3 dadr2 dadr1 dadr0 d/a control register 0 d/a data register 0 d/a data register 1 d/a data register 2 d/a data register 3 notation: dacr0: dadr0: dadr1: dadr2: dadr3: 310 13.1.3 pin configuration table 13-1 shows the pin configuration of the d/a converter. table 13-1 pin configuration name abbrev. i/o function analog power supply av cc input power supply and reference voltage of analog part analog ground av ss input ground and reference voltage of analog part analog output 0 da 0 output analog output channel 0 analog output 1 da 1 output analog output channel 1 analog output 2 da 2 output analog output channel 2 analog output 3 da 3 output analog output channel 3 13.1.4 register configuration table 13-2 shows the d/a converter register configuration. table 13-2 register configuration name abbrev. r/w initial value address d/a data register 0 dadr0 r/w h'00 h'ffc8 d/a data register 1 dadr1 r/w h'00 h'ffc9 d/a data register 2 dadr2 r/w h'00 h'ffca d/a data register 3 dadr3 r/w h'00 h'ffcb d/a control register 0 dacr0 r/w h'e0 h'ffcc 311 13.2 register descriptions 13.2.1 d/a data registers 3 to 0 (dadr3 to dadr0) d/a data registers 3 to 0 (dadr3 to dadr0) are 8-bit read/write registers that store the data to be converted for channels 3 to 0. in d/a conversion, the values in dadr3 to dadr0 are continuously converted and output at the analog output pins. upon reset, dadr3 to dadr0 are initialized to h'00. 13.3.2 d/a control register 0 (dacr0) dacr0 is an 8-bit read/write register that controls the operation of the d/a converter. upon reset and in standby mode, dacr0 is initialized to h'e0. bits 7 to 5: reserved bits bits 7 to 5 are reserved; they are always read as 1, and cannot be modified. bit 4: d/a enable 0 (dae0) bit 4 controls d/a conversion. when dae0 is cleared to 0, d/a conversion halts regardless of the settings of dadr3 to dadr0. if bits daoe3 to daoe0 are set to 1 in this state, an analog signal corresponding to d/a data h'00 is output from the corresponding pins. bit 4 dae0 description 0 d/a conversion halts on channels 3 to 0 (initial value) 1 d/a conversion is enabled on channels 3 to 0 bit initial value read/write 7 ? 1 r 6 ? 1 r 5 ? 1 r 4 dae0 0 r/w 3 daoe3 0 r/w 0 daoe0 0 r/w 2 daoe2 0 r/w 1 daoe1 0 r/w bit initial value read/write 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w 312 bit 3: d/a output enable 3 (daoe3) bit 3 enables analog output on channel 3. bit 3 daoe3 description 0 channel 3 analog output is disabled (initial value) (da 3 is in the high-impedance state) 1 channel 3 analog output is enabled bit 2: d/a output enable 2 (daoe2) bit 2 enables analog output on channel 2. bit 2 daoe2 description 0 channel 2 analog output is disabled (initial value) (da 2 is in the high-impedance state) 1 channel 2 analog output is enabled bit 1: d/a output enable 1 (daoe1) bit 1 enables analog output on channel 1. bit 1 daoe1 description 0 channel 1 analog output is disabled (initial value) (da 1 is in the high-impedance state) 1 channel 1 analog output is enabled bit 0: d/a output enable 0 (daoe0) bit 0 enables analog output on channel 0. bit 0 daoe0 description 0 channel 0 analog output is disabled (initial value) (da 0 is in the high-impedance state) 1 channel 0 analog output is enabled 313 13.3 operation each of the four channels has its own r-2r resistor ladder and carries out independent d/a conversion. an r-2r resistor ladder consists of resistor elements and eight switches controlled by the dadr bits (figure 13-2). when a dadr bit is set to 1, the corresponding switch connects to av cc and supplies a voltage for output at the da pin, the voltage depending on the bit. when two or more bits are set to 1, the sum of their voltages is output. example: output voltage when bits 7, 3, and 1 are set to 1 in dadr (dadr = h'8a) figure 13-2 circuit structure of d/a converter the procedure for d/a conversion is: 1. set the desired d/a data in dadr3 to dadr0. 2. in dacr0, set bit dae0 to 1, and set the daoe bits of the desired output channels to 1. d/a conversion will then start on all channels, and the converted results will be output from the da pins in the selected channels. sw 2r sw 2r sw 2r sw 2r sw 2r sw 2r sw 2r sw 2r r r r r r r r r r sw bit 6 av cc 4 bit 5 av cc 8 bit 4 av cc 16 bit 3 av cc 32 bit 2 av cc 64 bit 1 av cc 128 bit 0 av cc 256 av cc 2 bit 7 av ss av cc (dan) output (n = 0, 1, 2, or 3) dae0 daoe3 daoe2 daoe1 daoe0 dadrn (n = 0, 1, 2, or 3) note: the final output switch is controlled by bit daoe3, daoe2, daoe1, or daoe0 in dacr. = (1/2 + 1/32 + 1/128) av cc = (69/128) av cc bit 1 bit 3 bit 7 314 13.4 d/a converter operation states table 13-3 summarizes the d/a converter operation states. table 13-3 d/a converter operation states sub- sub- operation mode reset active sleep watch active sleep standby dadr3 to dadr0 reset functions functions functions functions functions retained dacr0 reset functions functions functions functions functions reset 13.5 application notes 1. connect the d/a output pins to an op-amp or other amplifier with high input impedance. connecting the d/a output pins to an amplifier with low input impedance will degrade d/a conversion accuracy. pulling these pins up or down through a resistance of a few hundred kilohms will also degrade conversion accuracy. 2. d/a conversion takes place whenever bit dae0 is set to 1. transition to standby mode automatically clears dae0 to 0, but transitions to the other power- down modes leave the dae0 setting unchanged. 315 section 14 electrical characteristics 14.1 absolute maximum ratings table 14-1 lists the absolute maximum ratings. table 14-1 absolute maximum ratings item symbol value unit power supply voltage v cc ?.3 to +7.0 v analog power supply voltage av cc ?.3 to +7.0 v programming voltage v pp ?.3 to +13.0 v input voltage ports other than ports b and c v in ?.3 to v cc +0.3 v ports b and c av in ?.3 to av cc +0.3 v operating temperature t opr ?0 to +75 ? storage temperature t stg ?5 to +125 ? note: permanent damage may occur to the chip if maximum ratings are exceeded. normal operation should be under the conditions specified in electrical characteristics. exceeding these values can result in incorrect operation and reduced reliability. 317 14.2 electrical characteristics 14.2.1 power supply voltage and operating range the power supply voltage and operating range are indicated by the shaded region in the figures below. 1. power supply voltage vs. oscillator frequency range 10.0 2.7 4.0 5.5 v (v) cc f (mhz) osc 32.768 2.7 4.0 5.5 v (v) cc fw (khz) ? active mode (high and medium speeds) sleep mode (high and medium speeds) all operating modes 5.0 2.0 * * 318 2. power supply voltage vs. clock frequency range 3. analog power supply voltage vs. a/d converter operating range note: * 2.5 v for the HD6433927, hd6433926, hd6433925, and hd6433924. 2.7 4.0 5.5 av (v) cc ?(mhz) ? active (high speed) mode sleep (high speed) mode 5.0 2.5 0.5 ? active (medium speed) mode sleep (medium speed) mode don? use in these modes. 78.125 2.7 4.0 5.5 v (v) cc ?(khz) h8/3877 series '93 14.2.1 (2) 5.0 2.7 4.0 5.5 v (v) cc ?(mhz) 16.384 2.7 4.0 5.5 v (v) cc ? (khz) sub ? active (high speed) mode sleep (high speed) mode (except cpu) ? ? subactive mode subsleep mode (except cpu) watch mode (except cpu) ? ? active (medium speed) mode sleep (medium speed) mode (except cpu) 8.192 4.096 2.5 0.5 39.0625 7.8125 * * 319 14.2.2 dc characteristics table 14-2 lists the dc characteristics. table 14-2 dc characteristics v cc = 4.0 v to 5.5 v, v ss = 0.0 v, t a = ?0? to +75 c unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes input high v ih res , nmi , 0.8 v cc v cc + 0.3 v voltage int 0 to int 7 , irq 0 to irq 3 , adtrg , tmib, tmiy, tmriv, tmciv, ftci, 0.9 v cc v cc + 0.3 v cc = 2.5 v to 5.5 v ftia, ftib, including subactive ftic, ftid, cs , mode sck 1 , sck 2 , tmic, trgv ud, si 1 , si 2 , 0.7 v cc v cc + 0.3 v p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , 0.8 v cc v cc + 0.3 v cc = 2.5 v to 5.5 v p6 0 to p6 7 , including subactive p7 0 to p7 7 , mode p8 0 to p8 7 pb 0 to pb 7 , 0.7 v cc av cc + 0.3 v pc 0 to pc 3 0.8 v cc av cc + 0.3 v cc = 2.5 v to 5.5 v including subactive mode osc 1 v cc ?0.5 v cc + 0.3 v v cc ?0.3 v cc + 0.3 v cc = 2.5 v to 5.5 v including subactive mode note: connect the test pin to v ss . 320 table 14-2 dc characteristics (cont) v cc = 4.0 v to 5.5 v, v ss = 0.0 v, t a = ?0? to +75? unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes input low v il res , nmi , ?.3 0.2 v cc v voltage int 0 to int 7 , irq 0 to irq3, adtrg , tmib, tmiy, tmriv, tmciv, ftci, ?.3 0.1 v cc v cc = 2.5 v to 5.5 v ftia, ftib, including subactive ftic, ftid, cs , mode sck 1 , sck 2 , tmic, trgv ud, si 1 , si 2 , ?.3 0.3 v cc v p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , ?.3 0.2 v cc v cc = 2.5 v to 5.5 v p7 0 to p7 7 , including subactive p8 0 to p8 7 , mode pb 0 to pb 7 , pc 0 to pc 3 osc 1 ?.3 0.5 v ?.3 0.3 v cc = 2.5 v to 5.5 v including subactive mode note: connect the test pin to v ss . 321 table 14-2 dc characteristics (cont) v cc = 4.0 v to 5.5 v, v ss = 0.0 v, t a = ?0? to +75 c unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes output v oh p1 0 to p1 7 , v cc ?1.0 v ? oh = 1.0 ma high p3 0 to p3 7 , voltage p4 0 to p4 7 , v cc ?1.0 ? oh = 1.5 ma p5 0 to p5 7 , p6 0 to p6 7 , v cc ?0.5 v cc = 2.5 v to 5.5 v p7 0 to p7 7 , ? oh = 0.1 ma p8 0 to p8 7 , rp 0 to rp 7 , tmov, ftoa, ftob, strb, so 1 , so 2 , tmow, tmoe, pwm output v ol p1 0 to p1 7 , 0.6 v i ol = 1.6 ma low p3 0 to p3 7 , voltage p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , 0.4 v cc = 2.5 v to 5.5 v p8 0 to p8 7 , i ol = 0.4 ma rp 0 to rp 7 , tmov, ftoa, ftob, strb, so 1 , so 2 , tmow, tmoe, pwm p4 0 to p4 7 1.0 v i ol = 10.0 ma 0.4 i ol = 1.6 ma 0.4 v cc = 2.5 v to 5.5 v i ol = 0.4 ma input/ | i il | int 0 to int 7 , 1 a v in = 0.5 v to output irq 0 to irq 3 , (v cc ?0.5 v) leakage adtrg , osc 1 , current ud, tmiv, tmiy, tmriv, tmciv, ftci, ftia, ftib, ftic, ftid, cs , si 1 , si 2 , sck 1 , sck 2 , tmic, trgv, p1 0 to p1 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 pb 0 to pb 7 , 1 v in = 0.5 v to pc 0 to pc 3 av cc ?0.5 v 322 table 14-2 dc characteristics (cont) v cc = 4.0 v to 5.5 v, v ss = 0.0 v, t a = ?0? to +75? unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes input | i il | res , nmi 20 a v in = 0.5 v to 2 leakage 1 (v cc ?0.5 v) 1 current open- i od so 1 , so 2 1 a v in = 0.5 v to drain (v cc ?0.5 v) leakage current pull-up ? p p1 0 to p1 7 , 50 300 a v cc = 5 v, mos p3 0 to p3 7 , v in = 0 v current p5 0 to p5 7 25 v cc = 2.7 v, reference v in = 0 v value input c in all input pins 15.0 pf f = 1 mhz, capacitance except power v in = 0 v, supply, res , t a = 25 c and nmi res 60.0 2 15.0 1 nmi 30.0 2 15.0 1 active i ope1 v cc 20 30 ma active (high- 3, 4 mode speed) mode current v cc = 5 v, dissipation f osc = 10 mhz i ope2 v cc 2 3 active (medium- 3, 4 speed) mode v cc = 5 v, f osc = 10 mhz sleep i sleep1 v cc 10 15 ma sleep (high- 3, 4 mode speed) mode current v cc = 5 v, dissipation f osc = 10 mhz i sleep2 v cc 2 3 sleep (medium- 3, 4 speed) mode v cc = 5 v, f osc = 10 mhz subactive i sub v cc 80 120 a v cc = 2.7 v 3, 4 mode 32-khz crystal current oscillator dissipation ( sub = ?/2) 30 v cc = 2.7 v 3, 4 32-khz crystal reference oscillator value ( sub = w /8) 323 table 14-2 dc characteristics (cont) v cc = 4.0 v to 5.5 v, v ss = 0.0 v, t a = ?0? to +75 c unless otherwise indicated. values item symbol applicable pins min typ max unit test condition notes subsleep i subsp v cc 20 60 a v cc = 2.7 v 3, 4 mode 32-khz crystal current oscillator dissipation ( sub = w /2) watch i watch v cc 6 a v cc = 2.7 v 3, 4 mode 32-khz crystal current oscillator dissipation standby i stby v cc 5 a 32-khz crystal 3, 4 mode oscillator not current used dissipation ram data v ram v cc 2 v 3, 4 retaining voltage notes: 1. applies to HD6433927, hd6433926, hd6433925, and hd6433924. 2. applies to hd6473927. 3. pin states during current measurement are given below. 4. excludes current in pull-up mos transistors and output buffers. mode res pin internal state other pins oscillator pins active (high-speed) v cc operates v cc system clock oscillator: mode ceramic or crystal active (medium-speed) subclock oscillator: mode pin x 1 = v cc sleep (high-speed) v cc only timers operate v cc mode sleep (medium-speed) mode subactive mode v cc operates v cc system clock oscillator: subsleep mode v cc only timers operate, v cc ceramic or crystal cpu stops subclock oscillator: watch mode v cc only time base v cc crystal perates, cpu stops standby mode v cc cpu and timers v cc system clock oscillator: both stop ceramic or crystal subclock oscillator: pin x 1 = v cc 324 table 14-2 dc characteristics (cont) v cc = 4.0 v to 5.5 v, v ss = 0.0 v, t a = ?0? to +75?, unless otherwise indicated. values item symbol min typ max unit allowable output output pins except port 4 i ol 2 ma low current (per pin) port 4 10 allowable output output pins except port 4 ? i ol 40 ma low current (total) port 4 80 allowable output all output pins ? oh 2 ma high current (per pin) allowable output all output pins ? (? oh ) 30 ma high current (total) 325 14.2.3 ac characteristics table 14-3 lists the control signal timing, and tables 14-4 and 14-5 list the serial interface timing. table 14-3 control signal timing v cc = 4.0 v to 5.5 v, v ss = 0.0 v, t a = ?0? to +75 c, unless otherwise specified. applicable values reference item symbol pins min typ max unit test condition figure system clock f osc osc 1 , osc 2 2 10 mhz oscillation frequency 2 5 v cc = 2.5 v to 5.5 v osc clock ( osc ) t osc osc 1 , osc 2 100 1000 ns 1 cycle time 200 1000 v cc = 2.5 v to 5.5 v figure 14-1 system clock (? t cyc 2 128 t osc v cc = 2.5 v to 5.5 v 1 cycle time 25.5 s subclock oscillation f w x 1 , x 2 32.768 khz v cc = 2.5 v to 5.5 v frequency watch clock ( w ) t w x 1 , x 2 30.5 s v cc = 2.5 v to 5.5 v cycle time subclock ( sub ) t subcyc 2 8 t w v cc = 2.5 v to 5.5 v 2 cycle time instruction cycle 2 t cyc v cc = 2.5 v to 5.5 v time t subcyc oscillation t rc osc 1 , osc 2 40 ms stabilization time 60 v cc = 2.5 v to 5.5 v (crystal oscillator) oscillation t rc osc 1 , osc 2 20 ms stabilization time 40 v cc = 2.5 v to 5.5 v (ceramic oscillator) oscillation t rc x 1 , x 2 2 s stabilization time external clock high t cph osc 1 40 ns figure 14-1 width 80 v cc = 2.5 v to 5.5 v external clock low t cpl osc 1 40 ns figure 14-1 width 80 v cc = 2.5 v to 5.5 v external clock rise t cpr 15 ns time 20 v cc = 2.5 v to 5.5 v external clock fall t cpf 15 ns time 20 v cc = 2.5 v to 5.5 v pin res low width t rel res 10 t cyc v cc = 2.5 v to 5.5 v figure 14-2 notes: 1. a frequency between 1 mhz to 10 mhz is required when an external clock is input. 2. selected with sa1 and sa0 of system clock control register 2 (syscr2). 326 table 14-3 control signal timing (cont) v cc = 4.0 v to 5.5 v, v ss = 0.0 v, t a = ?0? to +75?, unless otherwise specified. applicable values reference item symbol pins min typ max unit test condition figure input pin high width t ih nmi, 2 t cyc figure 14-3 irq 0 to irq 3 , t subcyc int 0 to int 7 , adtrg , tmib, tmiy, tmciv, tmic, tmriv, ftci, ftia, ftib, ftic, ftid, trgv input pin low width t il nmi , 2 t cyc figure 14-3 irq 0 to irq 3 , t subcyc int 0 to int 7 , adtrg , tmib, tmiy, tmciv, tmic, tmriv, ftci, ftia, ftib, ftic, ftid, trgv pin ud minimum t udh ud 4 t cyc figure 14-4 modulation width t udl t subcyc 327 table 14-4 serial interface (sci1, sci2) timing v cc = 4.0 v to 5.5 v, v ss = 0.0 v, t a = ?0? to +75 c, unless otherwise specified. applicable values reference item symbol pins min typ max unit test condition figure input serial clock t scyc sck 1 , sck 2 2 t cyc figure 14-5 cycle time input serial clock t sckh sck 1 , sck 2 0.4 t scyc high width input serial clock t sckl sck 1 , sck 2 0.4 t scyc low width input serial clock t sckr sck 1 , sck 2 60 ns rise time 80 v cc = 2.5 v to 5.5 v input serial clock t sckf sck 1 , sck 2 60 ns fall time 80 v cc = 2.5 v to 5.5 v serial output data t sod so 1 , so 2 200 ns delay time 350 v cc = 2.5 v to 5.5 v serial input data t sis si 1 , si 2 180 ns setup time 360 v cc = 2.5 v to 5.5 v serial input data t sih si 1 , si 2 180 ns hold time 360 v cc = 2.5 v to 5.5 v cs setup time t css cs 1 t scyc figure 14-6 cs hold time t csh cs 1 t scyc 328 14.2.4 a/d converter characteristics table 14-5 shows the a/d converter characteristics. table 14-5 a/d converter characteristics v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75?, unless otherwise specified. applicable values reference item symbol pins min typ max unit test condition figure analog power av cc av cc v cc ?0.3 v cc v cc + 0.3 v 1 supply voltage analog input av in an 0 to an 7 av ss av cc v voltage analog power ai cc av cc 1.5 ma av cc = 5 v supply current ai stop1 av cc 150 a 2 reference value ai stop2 av cc 5 a 3 analog input c ain an 0 to an 7 30 pf capacitance allowable r ain an 0 to 10 k signal source an 7 impedance resolution 8 bit absolute 2.5 lsb v cc = av cc = 5 v accuracy 2.5 lsb v cc = av cc = reference 4.0 v to 5.5 v value conversion 12.4 124 s time notes: 1. set av cc = v cc when the a/d converter is not used. 2. ai stop1 is the current in active and sleep modes while the a/d converter is idle. 3. ai stop2 is the current at reset and in standby, watch, subactive, and subsleep modes while the a/d converter is idle. 329 14.2.5 d/a converter characteristics table 14-6 shows the d/a converter characteristics. table 14-6 d/a converter characteristics v cc = 4.0 v to 5.5 v, av cc = 4.0 v to 5.5 v, v ss = av ss = 0.0 v, t a = ?0? to +75 c unless otherwise indicated. applicable values item symbol pins min typ max unit test condition notes analog power av cc av cc v cc ?0.3 v cc v cc + 0.3 v supply voltage analog output av out da 0 to da 3 av ss (255/256) v output open voltage av cc analog power ai cc av cc 8 ma av cc = 5 v, 1 supply current 1-m load ai stop 4 a 2 output r o da 0 to da 3 4 k resistance resolution 8 bit absolute 2 lsb v cc = av cc = 5 v accuracy data setup t su 3 s v cc = 5 v, 3 time f osc = 10 mhz figue 14-7 notes: 1. current value when all four channels are converting. 2. current value at reset or when bit dae0 is cleared to 0 in d/a control register 0 (dacr0). 3. data setup time (t su ): time until data has been transferred into d/a data register and analog output has stabilized. 330 14.3 operation timing figures 14-1 to 14-7 show timing diagrams. figure 14-1 system clock input timing figure 14-2 res low width figure 14-3 input timing v ih v il t il nmi irq 0 to irq 3 int 0 to int 7 adtrg tmib, ftia tmiy, ftib tmciv, ftic tmic, ftid tmriv ftci, trgv t ih h124 '92 h8/3834 u.m. 14.2 res v il t rel h124 '92 h8/3834 u.m. 14.1 t osc v ih v il t cph t cpl t cpr osc1 t cpf 331 figure 14-4 minimum ud high and low width ud v ih v il t udl t udh h124 '92 h8/3834 u.m. 14.4 332 figure 14-5 serial interface 1 and 2 input/output timing t scyc t sckf t sckl t sckh t sod v v oh ol * * t sis t sih sck sck so so si si 1 2 1 2 1 2 t sckr v or v ih oh * v or v il ol * notes: * output timing reference levels output high: output low: load conditions are shown in figure 14-8. v = 2.0 v v = 0.8 v oh ol 333 figure 14-6 serial interface 2 chip select timing figure 14-7 d/a converter output timing dadr0 dacr0 dao0 high impedance analog output high impedance t su max dadr dacr dadr dacr t css t csh v ih v il cs sck 2 v ih v il 334 14.4 output load circuit figure 14-8 output load condition v cc 2.4 k w 12 k w 30 pf h124 '92 h8/3834 u.m. 14.9 output pin 335 appendix a cpu instruction set a.1 instructions operation notation rd8/16 general register (destination) (8 or 16 bits) rs8/16 general register (source) (8 or 16 bits) rn8/16 general register (8 or 16 bits) ccr condition code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #xx: 3/8/16 immediate data (3, 8, or 16 bits) d: 8/16 displacement (8 or 16 bits) @aa: 8/16 absolute address (8 or 16 bits) + addition subtraction multiplication division logical and logical or ? exclusive logical or ? move logical complement condition code notation symbol modified according to the instruction result * not fixed (value not guaranteed) 0 always cleared to 0 not affected by the instruction execution result 337 table a-1 lists the h8/300l cpu instruction set. table a-1 instruction set mnemonic operation i h n z v c mov.b #xx:8, rd b #xx:8 ? rd8 2 ? ? 0 ? 2 mov.b rs, rd b rs8 ? rd8 2 ? ? 0 ? 2 mov.b @rs, rd b @rs16 ? rd8 2 ? ? 0 ? 4 mov.b @(d:16, rs), rd b @(d:16, rs16) ? rd8 4 ? ? 0 ? 6 mov.b @rs+, rd b @rs16 ? rd8 2 ? ? 0 ? 6 rs16+1 ? rs16 mov.b @aa:8, rd b @aa:8 ? rd8 2 ? ? 0 ? 4 mov.b @aa:16, rd b @aa:16 ? rd8 4 ? ? 0 ? 6 mov.b rs, @rd b rs8 ? @rd16 2 ? ? 0 ? 4 mov.b rs, @(d:16, rd) b rs8 ? @(d:16, rd16) 4 ? ? 0 ? 6 mov.b rs, @erd b rd16e1 ? rd16 2 ? ? 0 ? 6 rs8 ? @rd16 mov.b rs, @aa:8 b rs8 ? @aa:8 2 ? ? 0 ? 4 mov.b rs, @aa:16 b rs8 ? @aa:16 4 ? ? 0 ? 6 mov.w #xx:16, rd w #xx:16 ? rd 4 ? ? 0 ? 4 mov.w rs, rd w rs16 ? rd16 2 ? ? 0 ? 2 mov.w @rs, rd w @rs16 ? rd16 2 ? ? 0 ? 4 mov.w @(d:16, rs), rd w @(d:16, rs16) ? rd16 4 ? ? 0 ? 6 mov.w @rs+, rd w @rs16 ? rd16 2 ? ? 0 ? 6 rs16+2 ? rs16 mov.w @aa:16, rd w @aa:16 ? rd16 4 ? ? 0 ? 6 mov.w rs, @rd w rs16 ? @rd16 2 ? ? 0 ? 4 mov.w rs, @(d:16, rd) w rs16 ? @(d:16, rd16) 4 ? ? 0 ? 6 mov.w rs, @erd w rd16e2 ? rd16 2 ? ? 0 ? 6 rs16 ? @rd16 mov.w rs, @aa:16 w rs16 ? @aa:16 4 ? ? 0 ? 6 pop rd w @sp ? rd16 2 ? ? 0 ? 6 sp+2 ? sp push rs w spe2 ? sp 2 ? ? 0 ? 6 rs16 ? @sp 338 #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size table a-1 instruction set (cont) mnemonic operation i h n z v c eepmov if r4l 0 then 4 repeat @r5 ? @r6 r5+1 ? r5 r6+1 ? r6 r4le1 ? r4l until r4l=0 else next; add.b #xx:8, rd b rd8+#xx:8 ? rd8 2 ? 2 add.b rs, rd b rd8+rs8 ? rd8 2 ? 2 add.w rs, rd w rd16+rs16 ? rd16 2 ? 2 addx.b #xx:8, rd b rd8+#xx:8 +c ? rd8 2 ? 2 addx.b rs, rd b rd8+rs8 +c ? rd8 2 ? 2 adds.w #1, rd w rd16+1 ? rd16 2 ? ? ? ? ? ? 2 adds.w #2, rd w rd16+2 ? rd16 2 ? ? ? ? ? ? 2 inc.b rd b rd8+1 ? rd8 2 ? ? ? 2 daa.b rd b rd8 decimal adjust ? rd8 2 ? * * 2 sub.b rs, rd b rd8?s8 ? rd8 2 ? 2 sub.w rs, rd w rd16ers16 ? rd16 2 ? 2 subx.b #xx:8, rd b rd8e#xx:8 ec ? rd8 2 ? 2 subx.b rs, rd b rd8ers8 ec ? rd8 2 ? 2 subs.w #1, rd w rd16e1 ? rd16 2 ? ? ? ? ? ? 2 subs.w #2, rd w rd16e2 ? rd16 2 ? ? ? ? ? ? 2 dec.b rd b rd8e1 ? rd8 2 ? ? ? 2 das.b rd b rd8 decimal adjust ? rd8 2 ? * * 2 neg.b rd b 0?d ? rd 2 ? 2 cmp.b #xx:8, rd b rd8e#xx:8 2 ? 2 cmp.b rs, rd b rd8ers8 2 ? 2 cmp.w rs, rd w rd16ers16 2 ? 2 339 #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size table a-1 instruction set (cont) mnemonic operation i h n z v c mulxu.b rs, rd b rd8 rs8 ? rd16 2 ? ? ? ? ? ? 14 divxu.b rs, rd b rd16 ? rs8 ? rd16 2 ? ? ? ? ? ? 14 (rdh: remainder, rdl: quotient) and.b #xx:8, rd b rd8 #xx:8 ? rd8 2 ? ? 0 ? 2 and.b rs, rd b rd8 rs8 ? rd8 2 ? ? 0 ? 2 or.b #xx:8, rd b rd8 #xx:8 ? rd8 2 ? ? 0 ? 2 or.b rs, rd b rd8 rs8 ? rd8 2 ? ? 0 ? 2 xor.b #xx:8, rd b rd8 ? #xx:8 ? rd8 2 ? ? 0 ? 2 xor.b rs, rd b rd8 ? rs8 ? rd8 2 ? ? 0 ? 2 not.b rd b rd ? rd 2 ? ? 0 ? 2 shal.b rd b 2 ? ? 2 shar.b rd b 2 ? ? 0 2 shll.b rd b 2 ? ? 0 2 shlr.b rd b 2 ? ? 0 0 2 rotxl.b rd b 2 ? ? 0 2 rotxr.b rd b 2 ? ? 0 2 340 b 7 b 0 h8/3834 u.m '92 table a-2 shal, shll 0 c c b 7 b 0 h8/3834 u.m '92 table a-2 shar b 7 b 0 h8/3834 u.m '92 table a-2 shal, shll 0 c b 7 b 0 h8/3834 u.m '92 table a-2 shlr 0 c c b 7 b 0 h8/3834 u.m '92 table a-2 rotxl c b 7 b 0 h8/3834 u.m '92 table a-2 rotxr #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size table a-1 instruction set (cont) mnemonic operation i h n z v c rotl.b rd b 2 0 2 rotr.b rd b 2 0 2 bset #xx:3, rd b (#xx:3 of rd8) ? 1 2 ? ? ? ? ? ? 2 bset #xx:3, @rd b (#xx:3 of @rd16) ? 1 4 ? ? ? ? ? ? 8 bset #xx:3, @aa:8 b (#xx:3 of @aa:8) ? 1 4 ? ? ? ? ? ? 8 bset rn, rd b (rn8 of rd8) ? 1 2 ? ? ? ? ? ? 2 bset rn, @rd b (rn8 of @rd16) ? 1 4 ? ? ? ? ? ? 8 bset rn, @aa:8 b (rn8 of @aa:8) ? 1 4 ? ? ? ? ? ? 8 bclr #xx:3, rd b (#xx:3 of rd8) ? 0 2 ? ? ? ? ? ? 2 bclr #xx:3, @rd b (#xx:3 of @rd16) ? 0 4 ? ? ? ? ? ? 8 bclr #xx:3, @aa:8 b (#xx:3 of @aa:8) ? 0 4 ? ? ? ? ? ? 8 bclr rn, rd b (rn8 of rd8) ? 0 2 ? ? ? ? ? ? 2 bclr rn, @rd b (rn8 of @rd16) ? 0 4 ? ? ? ? ? ? 8 bclr rn, @aa:8 b (rn8 of @aa:8) ? 0 4 ? ? ? ? ? ? 8 bnot #xx:3, rd b (#xx:3 of rd8) ? 2 ? ? ? ? ? ? 2 ( #xx:3 of rd8 ) bnot #xx:3, @rd b (#xx:3 of @rd16) ? 4 ? ? ? ? ? ? 8 ( #xx:3 of @rd16 ) bnot #xx:3, @aa:8 b (#xx:3 of @aa:8) ? 4 ? ? ? ? ? ? 8 ( #xx:3 of @aa:8 ) bnot rn, rd b (rn8 of rd8) ? 2 ? ? ? ? ? ? 2 ( rn8 of rd8 ) bnot rn, @rd b (rn8 of @rd16) ? 4 ? ? ? ? ? ? 8 ( rn8 of @rd16 ) bnot rn, @aa:8 b (rn8 of @aa:8) ? 4 ? ? ? ? ? ? 8 ( rn8 of @aa:8 ) 341 #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size c b 7 b 0 h8/3834 u.m '92 table a-2 rotl c b 7 b 0 h8/3834 u.m '92 table a-2 rotr table a-1 instruction set (cont) mnemonic operation i h n z v c btst #xx:3, rd b ( #xx:3 of rd8 ) ? z 2 ? ? ? ? ? 2 btst #xx:3, @rd b ( #xx:3 of @rd16 ) ? z 4 ? ? ? ? ? 6 btst #xx:3, @aa:8 b ( #xx:3 of @aa:8 ) ? z 4 ? ? ? ? ? 6 btst rn, rd b ( rn8 of rd8 ) ? z 2 ? ? ? ? ? 2 btst rn, @rd b ( rn8 of @rd16 ) ? z 4 ? ? ? ? ? 6 btst rn, @aa:8 b ( rn8 of @aa:8 ) ? z 4 ? ? ? ? ? 6 bld #xx:3, rd b (#xx:3 of rd8) ? c 2 ? ? ? ? ? 2 bld #xx:3, @rd b (#xx:3 of @rd16) ? c 4 ? ? ? ? ? 6 bld #xx:3, @aa:8 b (#xx:3 of @aa:8) ? c 4 ? ? ? ? ? 6 bild #xx:3, rd b ( #xx:3 of rd8 ) ? c 2 ? ? ? ? ? 2 bild #xx:3, @rd b ( #xx:3 of @rd16 ) ? c 4 ? ? ? ? ? 6 bild #xx:3, @aa:8 b ( #xx:3 of @aa:8 ) ? c 4 ? ? ? ? ? 6 bst #xx:3, rd b c ? (#xx:3 of rd8) 2 ? ? ? ? ? ? 2 bst #xx:3, @rd b c ? (#xx:3 of @rd16) 4 ? ? ? ? ? ? 8 bst #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) 4 ? ? ? ? ? ? 8 bist #xx:3, rd b c ? (#xx:3 of rd8) 2 ? ? ? ? ? ? 2 bist #xx:3, @rd b c ? (#xx:3 of @rd16) 4 ? ? ? ? ? ? 8 bist #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) 4 ? ? ? ? ? ? 8 band #xx:3, rd b c (#xx:3 of rd8) ? c 2 ? ? ? ? ? 2 band #xx:3, @rd b c (#xx:3 of @rd16) ? c 4 ? ? ? ? ? 6 band #xx:3, @aa:8 b c (#xx:3 of @aa:8) ? c 4 ? ? ? ? ? 6 biand #xx:3, rd b c ( #xx:3 of rd8 ) ? c 2 ? ? ? ? ? 2 biand #xx:3, @rd b c ( #xx:3 of @rd16 ) ? c 4 ? ? ? ? ? 6 biand #xx:3, @aa:8 b c ( #xx:3 of @aa:8 ) ? c 4 ? ? ? ? ? 6 bor #xx:3, rd b c (#xx:3 of rd8) ? c 2 ? ? ? ? ? 2 bor #xx:3, @rd b c (#xx:3 of @rd16) ? c 4 ? ? ? ? ? 6 bor #xx:3, @aa:8 b c (#xx:3 of @aa:8) ? c 4 ? ? ? ? ? 6 bior #xx:3, rd b c ( #xx:3 of rd8 ) ? c 2 ? ? ? ? ? 2 bior #xx:3, @rd b c ( #xx:3 of @rd16 ) ? c 4 ? ? ? ? ? 6 342 #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size table a-1 instruction set (cont) mnemonic operation i h n z v c bior #xx:3, @aa:8 b c ( #xx:3 of @aa:8 ) ? c 4 ? ? ? ? ? 6 bxor #xx:3, rd b c ? (#xx:3 of rd8) ? c 2 ? ? ? ? ? 2 bxor #xx:3, @rd b c ? (#xx:3 of @rd16) ? c 4 ? ? ? ? ? 6 bxor #xx:3, @aa:8 b c ? (#xx:3 of @aa:8) ? c 4 ? ? ? ? ? 6 bixor #xx:3, rd b c ? ( #xx:3 of rd8 ) ? c 2 ? ? ? ? ? 2 bixor #xx:3, @rd b c ? ( #xx:3 of @rd16 ) ? c 4 ? ? ? ? ? 6 bixor #xx:3, @aa:8 b c ? ( #xx:3 of @aa:8 ) ? c 4 ? ? ? ? ? 6 bra d:8 (bt d:8) ? pc ? pc+d:8 2 ? ? ? ? ? ? 4 brn d:8 (bf d:8) ? pc ? pc+2 2 ? ? ? ? ? ? 4 bhi d:8 ? c z = 0 2 ? ? ? ? ? ? 4 bls d:8 ? c z = 1 2 ? ? ? ? ? ? 4 bcc d:8 (bhs d:8) ? c = 0 2 ? ? ? ? ? ? 4 bcs d:8 (blo d:8) ? c = 1 2 ? ? ? ? ? ? 4 bne d:8 ? z = 0 2 ? ? ? ? ? ? 4 beq d:8 ? z = 1 2 ? ? ? ? ? ? 4 bvc d:8 ? v = 0 2 ? ? ? ? ? ? 4 bvs d:8 ? v = 1 2 ? ? ? ? ? ? 4 bpl d:8 ? n = 0 2 ? ? ? ? ? ? 4 bmi d:8 ? n = 1 2 ? ? ? ? ? ? 4 bge d:8 ? n ? v = 0 2 ? ? ? ? ? ? 4 blt d:8 ? n ? v = 1 2 ? ? ? ? ? ? 4 bgt d:8 ? z (n ? v) = 0 2 ? ? ? ? ? ? 4 ble d:8 ? z (n ? v) = 1 2 ? ? ? ? ? ? 4 jmp @rn ? pc ? rn16 2 ? ? ? ? ? ? 4 jmp @aa:16 ? pc ? aa:16 4 ? ? ? ? ? ? 6 jmp @@aa:8 ? pc ? @aa:8 2 ? ? ? ? ? ? 8 bsr d:8 ? spe2 ? sp 2 ? ? ? ? ? ? 6 pc ? @sp pc ? pc+d:8 343 #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size if condition is true then pc ? pc+d:8 else next; branching condition table a-1 instruction set (cont) mnemonic operation i h n z v c jsr @rn sp? ? sp 2 ? ? ? ? ? ? 6 pc ? @sp pc ? rn16 jsr @aa:16 ? spe2 ? sp 4 ? ? ? ? ? ? 8 pc ? @sp pc ? aa:16 jsr @@aa:8 spe2 ? sp 2 ? ? ? ? ? ? 8 pc ? @sp pc ? @aa:8 rts ? pc ? @sp 2 ? ? ? ? ? ? 8 sp+2 ? sp rte ? ccr ? @sp 2 10 sp+2 ? sp pc ? @sp sp+2 ? sp sleep ? transit to sleep mode. 2 ? ? ? ? ? ? 2 ldc #xx:8, ccr b #xx:8 ? ccr 2 2 ldc rs, ccr b rs8 ? ccr 2 2 stc ccr, rd b ccr ? rd8 2 ? ? ? ? ? ? 2 andc #xx:8, ccr b ccr #xx:8 ? ccr 2 2 orc #xx:8, ccr b ccr #xx:8 ? ccr 2 2 xorc #xx:8, ccr b ccr ? #xx:8 ? ccr 2 2 nop ? pc ? pc+2 2 ? ? ? ? ? ? 2 notes: * the number of execution states given here assumes the opcode and operand data are in on-chip memory. for other cases see appendix a.3 below. set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. if the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. the number of states required for execution is 4n + 9 (n = value of r4l). set to 1 if the divisor is negative; otherwise cleared to 0. set to 1 if the divisor is zero; otherwise cleared to 0. 344 #xx: 8/16 rn @rn @(d:16, rn) @?n/@rn+ @aa: 8/16 @(d:8, pc) @@aa implied no. of states addressing mode/ instruction length (bytes) condition code operand size a.2 operation code map table a-2 is an operation code map. it shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. h8/350 u.m. '91 a.2 illust 345 high low 0 1 2 3 4 5 6 7 8 9 a b c d e f 0 1 2 3 4 5 6 7 8 9 a b c d e f nop bra mulxu bset shll shal sleep brn divxu bnot shlr shar stc bhi bclr rotxl rotl ldc bls btst rotxr rotr orc or bcc rts xorc xor bcs bsr bor bior bxor bixor band biand andc and bne rte ldc beq not neg bld bild bst bist add sub bvc bvs mov inc dec bpl jmp adds subs bmi eepmov mov cmp bge blt addx subx bgt jsr daa das ble mov add addx cmp subx or xor and mov mov * h8/3834 '92 table a-1 note: bit-manipulation instructions the push and pop instructions are identical in machine language to mov instructions. * table a-2 operation code map 346 a.3 number of execution states the tables here can be used to calculate the number of states required for instruction execution. table a-3 indicates the number of states required for each cycle (instruction fetch, branch address read, stack operation, byte data access, word data access, internal operation). table a-4 indicates the number of cycles of each type occurring in each instruction. the total number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: when instruction is fetched from on-chip rom, and an on-chip ram is accessed. bset #0, @ff00 from table a-4: i = l = 2, j = k = m = n= 0 from table a-3: s i = 2, s l = 2 number of states required for execution = 2 2 + 2 2 = 8 when instruction is fetched from on-chip rom, branch address is read from on-chip rom, and on- chip ram is used for stack area. jsr @@ 30 from table a-4: i = 2, j = k = 1, l = m = n = 0 from table a-3: s i = s j = s k = 2 number of states required for execution = 2 2 + 1 2+ 1 2 = 8 347 table a-3 number of cycles in each instruction execution status access location (instruction cycle) on-chip memory on-chip peripheral module instruction fetch s i 2 branch address read s j stack operation s k byte data access s l 2 or 3 * word data access s m internal operation s n 1 note: * depends on which on-chip module is accessed. see 2.9.1, notes on data access for details. 348 table a-4 number of cycles in each instruction instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n add add.b #xx:8, rd 1 add.b rs, rd 1 add.w rs, rd 1 adds adds.w #1, rd 1 adds.w #2, rd 1 addx addx.b #xx:8, rd 1 addx.b rs, rd 1 and and.b #xx:8, rd 1 and.b rs, rd 1 andc andc #xx:8, ccr 1 band band #xx:3, rd 1 band #xx:3, @rd 2 1 band #xx:3, @aa:8 2 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2 bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bclr bclr #xx:3, rd 1 bclr #xx:3, @rd 2 2 bclr #xx:3, @aa:8 2 2 bclr rn, rd 1 349 table a-4 number of cycles in each instruction (cont) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n bclr bclr rn, @rd 2 2 bclr rn, @aa:8 2 2 biand biand #xx:3, rd 1 biand #xx:3, @rd 2 1 biand #xx:3, @aa:8 2 1 bild bild #xx:3, rd 1 bild #xx:3, @rd 2 1 bild #xx:3, @aa:8 2 1 bior bior #xx:3, rd 1 bior #xx:3, @rd 2 1 bior #xx:3, @aa:8 2 1 bist bist #xx:3, rd 1 bist #xx:3, @rd 2 2 bist #xx:3, @aa:8 2 2 bixor bixor #xx:3, rd 1 bixor #xx:3, @rd 2 1 bixor #xx:3, @aa:8 2 1 bld bld #xx:3, rd 1 bld #xx:3, @rd 2 1 bld #xx:3, @aa:8 2 1 bnot bnot #xx:3, rd 1 bnot #xx:3, @rd 2 2 bnot #xx:3, @aa:8 2 2 bnot rn, rd 1 bnot rn, @rd 2 2 bnot rn, @aa:8 2 2 bor bor #xx:3, rd 1 bor #xx:3, @rd 2 1 bor #xx:3, @aa:8 2 1 bset bset #xx:3, rd 1 bset #xx:3, @rd 2 2 bset #xx:3, @aa:8 2 2 bset rn, rd 1 bset rn, @rd 2 2 350 table a-4 number of cycles in each instruction (cont) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n bset bset rn, @aa:8 2 2 bsr bsr d:8 2 1 bst bst #xx:3, rd 1 bst #xx:3, @rd 2 2 bst #xx:3, @aa:8 2 2 btst btst #xx:3, rd 1 btst #xx:3, @rd 2 1 btst #xx:3, @aa:8 2 1 btst rn, rd 1 btst rn, @rd 2 1 btst rn, @aa:8 2 1 bxor bxor #xx:3, rd 1 bxor #xx:3, @rd 2 1 bxor #xx:3, @aa:8 2 1 cmp cmp. b #xx:8, rd 1 cmp. b rs, rd 1 cmp.w rs, rd 1 daa daa.b rd 1 das das.b rd 1 dec dec.b rd 1 divxu divxu.b rs, rd 1 12 eepmov eepmov 2 2n+2* 1 inc inc.b rd 1 jmp jmp @rn 2 jmp @aa:16 2 2 jmp @@aa:8 2 1 2 jsr jsr @rn 2 1 jsr @aa:16 2 1 2 jsr @@aa:8 2 1 1 ldc ldc #xx:8, ccr 1 ldc rs, ccr 1 mov mov.b #xx:8, rd 1 mov.b rs, rd 1 mov.b @rs, rd 1 1 note: n: initial value in r4l. the source and destination operands are accessed n + 1 times each. 351 table a-4 number of cycles in each instruction (cont) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n mov mov.b @(d:16, rs), rd 2 1 mov.b @rs+, rd 1 1 2 mov.b @aa:8, rd 1 1 mov.b @aa:16, rd 2 1 mov.b rs, @rd 1 1 mov.b rs, @(d:16, rd) 2 1 mov.b rs, @?d 1 1 2 mov.b rs, @aa:8 1 1 mov.b rs, @aa:16 2 1 mov.w #xx:16, rd 2 mov.w rs, rd 1 mov.w @rs, rd 1 1 mov.w @(d:16, rs), rd 2 1 mov.w @rs+, rd 1 1 2 mov.w @aa:16, rd 2 1 mov.w rs, @rd 1 1 mov.w rs, @(d:16, rd) 2 1 mov.w rs, @?d 1 1 2 mov.w rs, @aa:16 2 1 mulxu mulxu.b rs, rd 1 12 neg neg.b rd 1 nop nop 1 not not.b rd 1 or or.b #xx:8, rd 1 or.b rs, rd 1 orc orc #xx:8, ccr 1 pop pop rd 1 1 2 push push rs 1 1 2 rotl rotl.b rd 1 rotr rotr.b rd 1 rotxl rotxl.b rd 1 rotxr rotxr.b rd 1 rte rte 2 2 2 rts rts 2 1 2 352 table a-4 number of cycles in each instruction (cont) instruction branch stack byte data word data internal fetch addr. read operation access access operation instruction mnemonic i j k l m n shll shll.b rd 1 shal shal.b rd 1 shar shar.b rd 1 shlr shlr.b rd 1 sleep sleep 1 stc stc ccr, rd 1 sub sub.b rs, rd 1 sub.w rs, rd 1 subs subs.w #1, rd 1 subs.w #2, rd 1 subx subx.b #xx:8, rd 1 subx.b rs, rd 1 xor xor.b #xx:8, rd 1 xor.b rs, rd 1 xorc xorc #xx:8, ccr 1 353 appendix b on-chip registers b.1 i/o registers (1) register bit names module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'f770 tier iciae icibe icice icide ociae ocibe ovie timer x h'f771 tcsrx icfa icfb icfc icfd ocfa ocfb ovf cclra h'f772 frch frch7 frch6 frch5 frch4 frch3 frch2 frch1 frch0 h'f773 frcl frcl7 frcl6 frcl5 frcl4 frcl3 frcl2 frcl1 frcl0 h'f774 ocrah/ ocrah7/ ocrah6/ ocrah5/ ocrah4/ ocrah3/ ocrah2/ ocrah1/ ocrah0/ ocrbh ocrbh7 ocrbh6 ocrbh5 ocrbh4 ocrbh3 ocrbh2 ocrbh1 ocrbh0 h'f775 ocral/ ocral7/ ocral6/ ocral5/ ocral4/ ocral3/ ocral2/ ocral1/ ocral0/ ocrbl ocrbl7 ocrbl6 ocrbl5 ocrbl4 ocrbl3 ocrbl2 ocrbl1 ocrbl0 h'f776 tcrx iedga iedgb iedgc iedgd bufea bufeb cks1 cks0 h'f777 tocr ocrs oea oeb olvla olvlb h'f778 icrah icrah7 icrah6 icrah5 icrah4 icrah3 icrah2 icrah1 icrah0 h'f779 icral icral7 icral6 icral5 icral4 icral3 icral2 icral1 icral0 f'f77a icrbh icrbh7 icrbh6 icrbh5 icrbh4 icrbh3 icrbh2 icrbh1 icrbh0 f'f77b icrbl icrbl7 icrbl6 icrbl5 icrbl4 icrbl3 icrbl2 icrbl1 icrbl0 h'f77c icrch icrch7 icrch6 icrch5 icrch4 icrch3 icrch2 icrch1 icrch0 h'f77d icrcl icrcl7 icrcl6 icrcl5 icrcl4 icrcl3 icrcl2 icrcl1 icrcl0 h'f77e icrdh icrdh7 icrdh6 icrdh5 icrdh4 icrdh3 icrdh2 icrdh1 icrdh0 h'f77f icrdl icrdl7 icrdl6 icrdl5 icrdl4 icrdl3 icrdl2 icrdl1 icrdl0 h'ffa0 scr1 snc1 snc0 cks3 cks2 cks1 cks0 sci1 h'ffa1 scsr1 sol orer stf h'ffa2 sdru sdru7 sdru6 sdru5 sdru4 sdru3 sdru2 sdru1 sdru0 h'ffa3 sdrl sdrl7 sdrl6 sdrl5 sdrl4 sdrl3 sdrl2 sdrl1 sdrl0 h'ffa4 star sta4 sta3 sta2 sta1 sta0 sci2 h'ffa5 edar eda4 eda3 eda2 eda1 eda0 h'ffa6 scr2 gap1 gap0 cks2 cks1 cks0 h'ffa7 scsr2 sol orer wt abt stf h'ffa8 h'ffa9 h'ffaa h'ffab notation sci1: serial communication interface 1 sci2: serial communication interface 2 354 register bit names module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'ffac h'ffad h'ffae h'ffaf h'ffb0 tma tma7 tma6 tma5 tma3 tma2 tma1 tma0 timer a h'ffb1 tca tca7 tca6 tca5 tca4 tca3 tca2 tca1 tca0 h'ffb2 tmb1 tmb17 tmb12 tmb11 tmb10 timer b1 h'ffb3 tcb1/ tcb17/ tcb16/ tcb15/ tcb14/ tcb13/ tcb12/ tcb11/ tcb10/ tlb1 tlb17 tlb16 tlb15 tlb14 tlb13 tlb12 tlb11 tlb10 h'ffb4 tmc tmc7 tmc6 tmc5 tmc2 tmc1 tmc0 timer c h'ffb5 tcc/ tcc7/ tcc6/ tcc5/ tcc4/ tcc3/ tcc2/ tcc1/ tcc0/ tlc tlc7 tlc6 tlc5 tlc4 tlc3 tlc2 tlc1 tlc0 h'ffb6 tme tme7 tmoeon ereq vrfr tme2 tme1 tme0 timer e h'ffb7 tce/ tce7/ tce6/ tce5/ tce4/ tce3/ tce2/ tce1/ tce0/ tle tle7 tle6 tle5 tle4 tle3 tle2 tle1 tle0 h'ffb8 tcrv0 cmieb cmiea ovie cclr1 cclr0 cks2 cks1 cks0 timer v h'ffb9 tcsrv cmfb cmfa ovf os3 os2 os1 os0 h'ffba tcora tcora7 tcora6 tcora5 tcora4 tcora3 tcora2 tcora1 tcora0 h'ffbb tcorb tcorb7 tcorb6 tcorb5 tcorb4 tcorb3 tcorb2 tcorb1 tcorb0 h'ffbc tcntv tcntv7 tcntv6 tcntv5 tcntv4 tcntv3 tcntv2 tcntv1 tcntv0 h'ffbd tcrv1 tveg1 tveg0 trge icks0 h'ffbe tcsrw b6wi tcwe b4wi tcsrwe b2wi wdon bowi wrst watchdog h'ffbf tcw tcw7 tcw6 tcw5 tcw4 tcw3 tcw2 tcw1 tcw0 timer h'ffc0 h'ffc1 h'ffc2 tmb2 tmb27 tmb22 tmb21 tmb20 timer b2 h'ffc3 tcb2/ tcb27/ tcb26/ tcb25/ tcb24/ tcb23/ tcb22/ tcb21/ tcb20/ tlb2 tlb27 tlb26 tlb25 tlb24 tlb23 tlb22 tlb21 tlb20 h'ffc4 amr cks trge ch3 ch2 ch1 ch0 a/d h'ffc5 adrr adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 converter h'ffc6 adsr adsf h'ffc7 h'ffc8 dadr0 dadr0 7 dadr0 6 dadr0 5 dadr0 4 dadr0 3 dadr0 2 dadr0 1 dadr0 0 d/a h'ffc9 dadr1 dadr1 7 dadr1 6 dadr1 5 dadr1 4 dadr1 3 dadr1 2 dadr1 1 dadr1 0 converter h'ffca dadr2 dadr2 7 dadr2 6 dadr2 5 dadr2 4 dadr2 3 dadr2 2 dadr2 1 dadr2 0 h'ffcb dadr3 dadr3 7 dadr3 6 dadr3 5 dadr3 4 dadr3 3 dadr3 2 dadr3 1 dadr3 0 355 register bit names module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'ffcc dacr0 daeo daoe 3 daoe 2 daoe 1 daoe 0 d/a converter h'ffcd tmy tmy 7 tmy 2 tmy 1 tmy 0 timer y h'ffce tcyh/ tcyh 7 / tcyh 6 / tcyh 5 / tcyh 4 / tcyh 3 / tcyh 2 / tcyh 1 / tcyh 0 / tlyh tlyh 7 tlyh 6 tlyh 5 tlyh 4 tlyh 3 tlyh 2 tlyh 1 tlyh 0 h'ffcf tcyl/ tcyl 7 / tcyl 6 / tcyl 5 / tcyl 4 / tcyl 3 / tcyl 2 / tcyl 1 / tcyl 0 / tlyl tlyl 7 tlyl 6 tlyl 5 tlyl 4 tlyl 3 tlyl 2 tlyl 1 tlyl 0 h'ffd0 pwcr pwcr 0 14-bit h'ffd1 pwdru pwdru 5 pwdru 4 pwdru 3 pwdru 2 pwdru 1 pwdru 0 pwm h'ffd2 pwdrl pwdrl 7 pwdrl 6 pwdrl 5 pwdrl 4 pwdrl 3 pwdrl 2 pwdrl 1 pwdrl 0 h'ffd3 h'ffd4 pdr1 p1 7 p1 6 p1 5 p1 4 p1 3 p1 2 p1 1 p1 0 i/o ports h'ffd5 h'ffd6 pdr3 p3 7 p3 6 p3 5 p3 4 p3 3 p3 2 p3 1 p3 0 i/o ports h'ffd7 pdr4 p4 7 p4 6 p4 5 p4 4 p4 3 p4 2 p4 1 p4 0 h'ffd8 pdr5 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 h'ffd9 pdr6 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 h'ffda pdr7 p7 7 p7 6 p7 5 p7 4 p7 3 p7 2 p7 1 p7 0 h'ffdb pdr8 p8 7 p8 6 p8 5 p8 4 p8 3 p8 2 p8 1 p8 0 h'ffdc h'ffdd pdrb pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 i/o ports h'ffde pdrc pc 3 pc 2 pc 1 pc 0 h'ffdf h'ffe0 h'ffe1 h'ffe2 tmb3 tmb3 7 tmb3 2 tmb3 1 tmb3 0 timer b3 h'ffe3 tcb3/ tcb3 7 / tcb3 6 / tcb3 5 / tcb3 4 / tcb3 3 / tcb3 2 / tcb3 1 / tcb3 0 / tlb3 tlb3 7 tlb3 6 tlb3 5 tlb3 4 tlb3 3 tlb3 2 tlb3 1 tlb3 0 h'ffe4 pcr1 pcr1 7 pcr1 6 pcr1 5 pcr1 4 pcr1 3 pcr1 2 pcr1 1 pcr1 0 i/o ports h'ffe5 h'ffe6 pcr3 pcr3 7 pcr3 6 pcr3 5 pcr3 4 pcr3 3 pcr3 2 pcr3 1 pcr3 0 i/o ports h'ffe7 pcr4 pcr4 7 pcr4 6 pcr4 5 pcr4 4 pcr4 3 pcr4 2 pcr4 1 pcr4 0 h'ffe8 pcr5 pcr5 7 pcr5 6 pcr5 5 pcr5 4 pcr5 3 pcr5 2 pcr5 1 pcr5 0 h'ffe9 pcr6 pcr6 7 pcr6 6 pcr6 5 pcr6 4 pcr6 3 pcr6 2 pcr6 1 pcr6 0 h'ffea pcr7 pcr7 7 pcr7 6 pcr7 5 pcr7 4 pcr7 3 pcr7 2 pcr7 1 pcr7 0 h'ffeb pcr8 pcr8 7 pcr8 6 pcr8 5 pcr8 4 pcr8 3 pcr8 2 pcr8 1 pcr8 0 h'ffec 356 register bit names module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 name h'ffed pucr1 pucr1 7 pucr1 6 pucr1 5 pucr1 4 pucr1 3 pucr1 2 pucr1 1 pucr1 0 i/o ports h'ffee pucr3 pucr3 7 pucr3 6 pucr3 5 pucr3 4 pucr3 3 pucr3 2 pucr3 1 pucr3 0 h'ffef pucr5 pucr5 7 pucr5 6 pucr5 5 pucr5 4 pucr5 3 pucr5 2 pucr5 1 pucr5 0 h'fff0 syscr1 ssby sts2 sts1 sts0 lson system h'fff1 syscr2 nesel dton mson sa1 sa0 control h'fff2 iegr1 nmieg ieg3 ieg2 ieg1 ieg0 h'fff3 iegr2 integ 7 integ 6 integ 5 integ 4 integ 3 integ 2 integ 1 integ 0 h'fff4 ienr1 ientb1 ienta ienty ien3 ien2 ien1 ien0 h'fff5 ienr2 iendt ienad iens2 iensi iente ientc ientb3 ientb2 h'fff6 ienr3 inten7 inten6 inten5 inten4 inten3 inten2 inten1 inten0 h'fff7 irr1 irrtb1 irrta irrty irri3 irri2 irri1 irri0 h'fff8 irr2 irrdt irrad irrs2 irrs1 irrte irrtc irrtb3 irrtb2 h'fff9 irr3 intf 7 intf 6 intf 5 intf 4 intf 3 intf 2 intf 1 intf 0 h'fffa h'fffb h'fffc pmr1 irq3 irq2 irq1 pwm tciceg tmoe tmow i/o ports h'fffd pmr3 cs strb so2 si2 sck2 so1 si1 sck1 h'fffe rter rter 7 rter 6 rter 5 rter 4 rter 3 rter 2 rter 1 rter 0 h'ffff pmr7 pof2 pof1 357 b.2 i/o registers (2) h8/3003 u.m. '93 b.2 tmc?imer mode register c h'b4 timer c register name address to which the register is mapped name of on-chip supporting module register acronym bit numbers initial bit values names of the bits. dashes (? indicate reserved bits. full name of bit descriptions of bit settings read only write only read and write r w r/w possible types of access bit initial value read/write 7 tmc7 0 r/w 6 tmc6 0 r/w 5 tmc5 0 r/w 3 1 0 tmc0 0 r/w 2 tmc2 0 r/w 1 tmc1 0 r/w 4 1 clock select 0 internal clock: internal clock: 0 0 1 internal clock: internal clock: 1 0 1 1 0 0 1 1 0 1 internal clock: internal clock: internal clock: external event (tmic): ?8192 ?2048 ?512 ?64 ?16 ?4 ? /4 rising or falling edge w counter up/down control tcc is an up-counter tcc is a down-counter 0 0 1 tcc up/down control is determined by input at pin ud. tcc is a down-counter if the ud input is high, and an up-counter if the ud input is low. 1 * 358 tier?imer interrupt enable register h'f770 timer x bit initial value read/write 7 iciae 0 r/w 6 icibe 0 r/w 5 icice 0 r/w 4 icide 0 r/w 3 ociae 0 r/w 0 ? 1 2 ocibe 0 r/w 1 ovie 0 r/w timer overflow interrupt enable 0 interrupt request (fovi) by ovf is disabled interrupt request (fovi) by ovf is enabled 1 output compare interrupt b enable 0 nterrupt request (ocib) by ocfb is disabled interrupt request (ocib) by ocfb is enabled 1 output compare interrupt a enable 0 interrupt request (ocia) by ocfa is disabled interrupt request (ocia) by ocfa is enabled 1 input capture interrupt d enable 0 interrupt request (icid) by icfd is disabled interrupt request (icid) by icfd is enabled 1 input capture interrupt c enable 0 interrupt request (icic) by icfc is disabled interrupt request (icic) by icfc is enabled 1 input capture interrupt b enable 0 interrupt request (icib) by icfb is disabled interrupt request (icib) by icfb is enabled 1 input capture interrupt a enable 0 interrupt request (icia) by icfa is disabled interrupt request (icia) by icfa is enabled 1 359 tcsrx?imer control/status register x h'f771 timer x bit initial value read/write 7 icfa 0 r/(w) 6 icfb 0 r/(w) 5 icfc 0 r/(w) 4 icfd 0 r/(w) 3 ocfa 0 r/(w) 0 cclra 0 r/w 2 ocfb 0 r/(w) 1 ovf 0 r/(w) * * * * * * * 0 [clearing condition] after reading ovf = 1, cleared by writing 0 to ovf timer overflow 1 [setting condition] set when the frc value goes from h'ffff to h'0000 0 frc is not cleared by compare match a counter clear a 1 frc is cleared by compare match a 0 [clearing condition] after reading ocfb = 1, cleared by writing 0 to ocfb output compare flag b 1 [setting condition] set when frc matches ocrb 0 [clearing condition] after reading ocfa = 1, cleared by writing 0 to ocfa output compare flag a 1 [setting condition] set when frc matches ocra 0 [clearing condition] after reading icfd = 1, cleared by writing 0 to icfd input capture flag d 1 [setting condition] set by input capture signal 0 [clearing condition] after reading icfc = 1, cleared by writing 0 to icfc input capture flag c 1 [setting condition] set by input capture signal 0 [clearing condition] after reading icfb = 1, cleared by writing 0 to icfb input capture flag b 1 [setting condition] set on transfer to icrb by input capture signal 0 [clearing condition] after reading icfa = 1, cleared by writing 0 to icfa input capture flag a 1 [setting condition] set on transfer to icra by input capture signal note: * only a write of 0 for flag clearing is possible. 360 frch?ree-running counter h h'f772 timer x frcl?ree-running counter l h'f773 timer x ocrah?utput compare register ah h'f774 timer x ocrbh?utput compare register bh h'f774 timer x bit initial value read/write 7 ocrbh7 1 r/w 6 ocrbh6 1 r/w 5 ocrbh5 1 r/w 4 ocrbh4 1 r/w 3 ocrbh3 1 r/w 0 ocrbh0 1 r/w 2 ocrbh2 1 r/w 1 ocrbh1 1 r/w bit initial value read/write 7 ocrah7 1 r/w 6 ocrah6 1 r/w 5 ocrah5 1 r/w 4 ocrah4 1 r/w 3 ocrah3 1 r/w 0 ocrah0 1 r/w 2 ocrah2 1 r/w 1 ocrah1 1 r/w bit initial value read/write 7 frcl7 0 r/w 6 frcl6 0 r/w 5 frcl5 0 r/w 4 frcl4 0 r/w 3 frcl3 0 r/w 0 frcl0 0 r/w 2 frcl2 0 r/w 1 frcl1 0 r/w count value bit initial value read/write 7 frch7 0 r/w 6 frch6 0 r/w 5 frch5 0 r/w 4 frch4 0 r/w 3 frch3 0 r/w 0 frch0 0 r/w 2 frch2 0 r/w 1 frch1 0 r/w count value 361 ocral?utput compare register al h'f775 timer x ocrbl?utput compare register bl h'f775 timer x bit initial value read/write 7 ocrbl7 1 r/w 6 ocrbl6 1 r/w 5 ocrbl5 1 r/w 4 ocrbl4 1 r/w 3 ocrbl3 1 r/w 0 ocrbl0 1 r/w 2 ocrbl2 1 r/w 1 ocrbl1 1 r/w bit initial value read/write 7 ocral7 1 r/w 6 ocral6 1 r/w 5 ocral5 1 r/w 4 ocral4 1 r/w 3 ocral3 1 r/w 0 ocral0 1 r/w 2 ocral2 1 r/w 1 ocral1 1 r/w 362 tcrx?imer control register x h'f776 timer x bit initial value read/write 7 iedga 0 r/w 6 iedgb 0 r/w 5 iedgc 0 r/w 4 iedgd 0 r/w 3 bufea 0 r/w 0 cks0 0 r/w 2 bufeb 0 r/w 1 cks1 0 r/w clock select 0 1 internal clock: ?2 internal clock: ?8 internal clock: ?32 external clock: rising edge 0 1 0 1 buffer enable b 0 icrd is not used as a buffer register for icrb icrd is used as a buffer register for icrb 1 buffer enable a 0 icrc is not used as a buffer register for icra icrc is used as a buffer register for icra 1 input edge select d 0 falling edge of input d is captured rising edge of input d is captured 1 input edge select c 0 falling edge of input c is captured rising edge of input c is captured 1 input edge select b 0 falling edge of input b is captured rising edge of input b is captured 1 input edge select a 0 falling edge of input a is captured rising edge of input a is captured 1 363 tocr?utput compare control register h'f777 timer x bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 4 ocrs 0 r/w 3 oea 0 r/w 0 olvlb 0 r/w 2 oeb 0 r/w 1 olvla 0 r/w output level b 0 low level high level 1 output level a 0 low level high level 1 output enable b 0 output compare b output is disabled output compare b output is enabled 1 output enable a 0 output compare a output is disabled output compare a output is enabled 1 output compare register select 0 ocra is selected ocrb is selected 1 364 icrah?nput capture register ah h'f778 timer x icral?nput capture register al h'f779 timer x icrbh?nput capture register bh h'f77a timer x icrbl?nput capture register bl h'f77b timer x bit initial value read/write 7 icrbl7 0 r 6 icrbl6 0 r 5 icrbl5 0 r 4 icrbl4 0 r 3 icrbl3 0 r 0 icrbl0 0 r 2 icrbl2 0 r 1 icrbl1 0 r bit initial value read/write 7 icrbh7 0 r 6 icrbh6 0 r 5 icrbh5 0 r 4 icrbh4 0 r 3 icrbh3 0 r 0 icrbh0 0 r 2 icrbh2 0 r 1 icrbh1 0 r bit initial value read/write 7 icral7 0 r 6 icral6 0 r 5 icral5 0 r 4 icral4 0 r 3 icral3 0 r 0 icral0 0 r 2 icral2 0 r 1 icral1 0 r bit initial value read/write 7 icrah7 0 r 6 icrah6 0 r 5 icrah5 0 r 4 icrah4 0 r 3 icrah3 0 r 0 icrah0 0 r 2 icrah2 0 r 1 icrah1 0 r 365 icrch?nput capture register ch h'f77c timer x icrcl?nput capture register cl h'f77d timer x icrdh?nput capture register dh h'f77e timer x icrdl?nput capture register dl h'f77f timer x bit initial value read/write 7 icrdl7 0 r 6 icrdl6 0 r 5 icrdl5 0 r 4 icrdl4 0 r 3 icrdl3 0 r 0 icrdl0 0 r 2 icrdl2 0 r 1 icrdl1 0 r bit initial value read/write 7 icrdh7 0 r 6 icrdh6 0 r 5 icrdh5 0 r 4 icrdh4 0 r 3 icrdh3 0 r 0 icrdh0 0 r 2 icrdh2 0 r 1 icrdh1 0 r bit initial value read/write 7 icrcl7 0 r 6 icrcl6 0 r 5 icrcl5 0 r 4 icrcl4 0 r 3 icrcl3 0 r 0 icrcl0 0 r 2 icrcl2 0 r 1 icrcl1 0 r bit initial value read/write 7 icrch7 0 r 6 icrch6 0 r 5 icrch5 0 r 4 icrch4 0 r 3 icrch3 0 r 0 icrch0 0 r 2 icrch2 0 r 1 icrch1 0 r 366 scr1?erial control register 1 h'ffa0 sci1 bit initial value read/write 7 snc1 0 r/w 6 snc0 0 r/w 5 ? 0 r/w 4 ? 0 r/w 3 cks3 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w operation mode select clock source select 0 clock source is prescaler s, and pin sck is output pin 1 clock source is external clock, and pin sck is input pin 0 8-bit synchronous transfer mode 16-bit synchronous transfer mode 1 0 1 0 1 continuous clock output mode reserved clock select (cks2 to cks0) bit 2 cks2 cks1 cks0 bit 1 bit 0 0 ?1024 ?256 1 1 0 ?64 ?32 1 ?16 1 0 0 1 ?8 0 0 ?4 1 0 1 ?2 ?= 5 mhz 204.8 ? 51.2 ? 12.8 ? 6.4 ? 3.2 ? 1.6 ? 0.8 ? ?= 2.5 mhz 409.6 ? 102.4 ? 25.6 ? 12.8 ? 6.4 ? 3.2 ? 1.6 ? 0.8 ? synchronous serial clock cycle 1 1 prescaler division 367 scsr1?erial control/status register 1 h'ffa1 sci1 bit initial value read/write 7 ? 1 6 sol 0 r/w 5 orer 0 r/(w) 4 ? 0 3 ? 0 0 stf 0 r/w 2 ? 0 1 ? 0 extended data bit overrun error flag * start flag 0 indicates that transfer is stopped invalid 1 read write read write indicates transfer in progress starts a transfer operation note: only a write of 0 for flag clearing is possible. * 0 [clearing condition] after reading 1, cleared by writing 0 1 [setting condition] set if a clock pulse is input after transfer is complete, when an external clock is used 0 so 1 pin output level is low so 1 pin output level changes to low so 1 pin output level is high so 1 pin output level changes to high 1 read write read write 368 sdru?erial data register u h'ffa2 sci1 sdrl?erial data register l h'ffa3 sci1 star?tart address register h'ffa4 sci2 h8/3834 u.m. '93 star (h'a4) bit initial value read/write 7 1 6 1 5 1 4 sta4 0 r/w 3 sta3 0 r/w 0 sta0 0 r/w 2 sta2 0 r/w 1 sta1 0 r/w transfer start address in range from h'ff80 to h'ff9f h8/3834 u.m. '93 sdrl (h'a3) bit initial value read/write 7 sdrl7 not fixed r/w 6 sdrl6 not fixed r/w 5 sdrl5 not fixed r/w 4 sdrl4 not fixed r/w 3 sdrl3 not fixed r/w 0 sdrl0 not fixed r/w 2 sdrl2 not fixed r/w 1 sdrl1 not fixed r/w stores transmit and receive data 8-bit transfer mode: 16-bit transfer mode: 8-bit data lower 8 bits of data h8/3834 u.m. '93 sdru (h'a2) bit initial value read/write 7 sdru7 not fixed r/w 6 sdru6 not fixed r/w 5 sdru5 not fixed r/w 4 sdru4 not fixed r/w 3 sdru3 not fixed r/w 0 sdru0 not fixed r/w 2 sdru2 not fixed r/w 1 sdru1 not fixed r/w stores transmit and receive data 8-bit transfer mode: 16-bit transfer mode: not used upper 8 bits of data 369 edar?nd address register h'ffa5 sci2 scr2?erial control register 2 h'ffa6 sci2 bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 4 gap1 0 r/w 3 gap0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w gap select 0 no gaps between bytes a gap of 8 clock cycles is inserted between bytes 1 0 1 0 1 a gap of 24 clock cycles is inserted between bytes a gap of 56 clock cycles is inserted between bytes clock select (cks2 to cks0) bit 2 cks2 cks1 cks0 bit 1 bit 0 0 sck output 1 1 0 1 1 0 0 1 0 0 1 0 1 sck input ?= 5 mhz 51.2 ? 12.8 ? 6.4 ? 3.2 ? 1.6 ? 0.8 ? ?= 2.5 mhz 102.4 ? 25.6 ? 12.8 ? 6.4 ? 3.2 ? 1.6 ? 0.8 ? serial clock cycle pin sck ?256 ?64 ?32 ?16 ?8 ?4 ?2 prescaler division 2 2 prescaler s external clock clock source 2 h8/3834 u.m. '93 edar (h'45) bit initial value read/write 7 1 6 1 5 1 4 eda4 0 r/w 3 eda3 0 r/w 0 eda0 0 r/w 2 eda2 0 r/w 1 eda1 0 r/w transfer end address in range from h'ff80 to h'ff9f 370 scsr2?erial control/status register 2 h'ffa7 sci2 bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 4 sol 0 r/w 3 orer 0 r/(w) 0 stf 0 r/w 2 wt 0 r/(w) 1 abt 0 r/(w) extended data bit abort flag * start flag note: only a write of 0 for flag clearing is possible. * * * wait flag overrun error flag 0 [clearing condition] after reading 1, cleared by writing 0 1 [setting condition] when cs goes high during a transfer 0 [clearing condition] after reading 1, cleared by writing 0 1 [setting condition] an attempt was made to read or write the (32-byte) serial data buffer during a transfer or while waiting for cs input 0 [clearing condition] after reading 1, cleared by writing 0 1 [setting condition] set if a clock pulse is input after transfer is complete, when an external clock is used 0 indicates that transfer is stopped stops a transfer operation 1 read write read write indicates transfer in progress or waiting for cs input starts a transfer operation 0 so 2 pin output level is low so 2 pin output level changes to low so 2 pin output level is high so 2 pin output level changes to high 1 read write read write 371 tma?imer mode register a h'ffb0 timer a h8/3843 u.m. '93 tma (h'b0) bit initial value read/write 7 tma7 0 r/w 6 tma6 0 r/w 5 tma5 0 r/w 0 tma0 0 r/w 2 tma2 0 r/w 1 tma1 0 r/w internal clock select tma3 tma2 0 pss pss pss pss 0 4 1 clock output select 0 ?32 ?16 tma1 0 1 tma0 0 0 1 1 pss pss pss pss 1 0 1 0 0 1 1 1 psw psw psw psw 0 0 1 0 0 1 1 psw and tca are reset 1 0 1 0 0 1 1 prescaler and divider ratio or overflow period ?8192 ?4096 ?2048 ?512 ?256 ?128 ?32 ?8 1 s 0.5 s 0.25 s 0.03125 s interval timer time base function 0 0 1 ?8 ?4 1 0 1 1 0 0 1 1 0 1 ? /32 w ? /16 w ? /8 w ? /4 w 3 tma3 0 r/w 372 tca?imer counter a h'ffb1 timer a tmb1?imer mode register b1 h'ffb2 timer b1 bit initial value read/write 7 tmb17 0 r/w 6 ? 1 5 ? 1 3 ? 1 0 tmb10 0 r/w 2 tmb12 0 r/w 1 tmb11 0 r/w 4 ? 1 auto-reload function select clock select 0 internal clock: internal clock: 0 0 1 internal clock: internal clock: 1 0 1 1 0 0 1 1 0 1 internal clock: internal clock: internal clock: external event (tmib): ?8192 ?2048 ?512 ?256 ?64 ?16 ?4 rising or falling edge 0 interval timer function selected 1 auto-reload function selected h8/3843 u.m. '93 tca (h'b1) bit initial value read/write 7 tca7 0 r 6 tca6 0 r 5 tca5 0 r 4 tca4 0 r 3 tca3 0 r 0 tca0 0 r 2 tca2 0 r 1 tca1 0 r count value 373 tcb1?imer counter b1 h'ffb3 timer b1 tlb1?imer load register b1 h'ffb3 timer b1 bit initial value read/write 7 tlb17 0 w 6 tlb16 0 w 5 tlb15 0 w 4 tlb14 0 w 3 tlb13 0 w 0 tlb10 0 w 2 tlb12 0 w 1 tlb11 0 w reload value bit initial value read/write 7 tcb17 0 r 6 tcb16 0 r 5 tcb15 0 r 4 tcb14 0 r 3 tcb13 0 r 0 tcb10 0 r 2 tcb12 0 r 1 tcb11 0 r count value 374 tmc?imer mode register c h'ffb4 timer c tcc?imer counter c h'ffb5 timer c h8/3843 u.m. '93 tcc (h'b5) bit initial value read/write 7 tcc7 0 r 6 tcc6 0 r 5 tcc5 0 r 4 tcc4 0 r 3 tcc3 0 r 0 tcc0 0 r 2 tcc2 0 r 1 tcc1 0 r count value h8/3843 u.m. '93 tmc (h'b4) bit initial value read/write 7 tmc7 0 r/w 6 tmc6 0 r/w 5 tmc5 0 r/w 3 1 0 tmc0 0 r/w 2 tmc2 0 r/w 1 tmc1 0 r/w 4 1 auto-reload function select clock select 0 internal clock: internal clock: 0 0 1 internal clock: internal clock: 1 0 1 1 0 0 1 1 0 1 internal clock: internal clock: internal clock: external event (tmic): ?8192 ?2048 ?512 ?64 ?16 ?4 ? /4 rising or falling edge 0 interval timer function selected 1 auto-reload function selected w counter up/down control tcc is an up-counter tcc is a down-counter 0 0 1 tcc up/down control is determined by input at pin ud. tcc is a down-counter if the ud input is high, and an up-counter if the ud input is low. 1 * note: don? care * 375 376 tlc?imer load register c h'ffb5 timer c tme?imer mode register e h'ffb6 timer e bit initial value read/write 7 tme7 0 r/w 6 tmoeon 0 r/w 5 ereq 0 r/w 3 ? 1 0 tme0 0 r/w 2 tme2 0 r/w 1 tme1 0 r/w 4 vrfr 0 r/w auto-reload function select clock select 0 internal clock: ?8192 internal clock: ?4096 internal clock: ?2048 internal clock: ?512 internal clock: ?256 internal clock: ?128 internal clock: ?32 internal clock: ?8 0 0 1 1 0 1 1 0 0 1 1 0 1 0 interval timer function selected auto-reload function selected 1 bit 6: timer e output on/off bit 5: fixed frequency select bit 4: variable frequency select description bit 6 tmoeon bit 5 ereq low level output bit 4 vrfr fixed-frequency output (?2048): 1.95 khz (?= 4 mhz), 0.98 khz (?= 2 mhz) 0 * * 1 0 0 fixed-frequency output (?1024): 3.9 khz (?= 4 mhz), 1.95 khz (?= 2 mhz) 1 0 variable-frequency output: toggles at timer e overflow * 1 h8/3843 u.m. '93 tlc (h'b5) bit initial value read/write 7 tlc7 0 w 6 tlc6 0 w 5 tlc5 0 w 4 tlc4 0 w 3 tlc3 0 w 0 tlc0 0 w 2 tlc2 0 w 1 tlc1 0 w reload value tce?imer counter e h'ffb7 timer e tle?imer load e h'ffb7 timer e bit initial value read/write 7 tle7 0 w 6 tle6 0 w 5 tle5 0 w 4 tle4 0 w 3 tle3 0 w 0 tle0 0 w 2 tle2 0 w 1 tle1 0 w reload value bit initial value read/write 7 tce7 0 r 6 tce6 0 r 5 tce5 0 r 4 tce4 0 r 3 tce3 0 r 0 tce0 0 r 2 tce2 0 r 1 tce1 0 r count value 377 tcrv0?imer control register v0 h'ffb8 timer v bit initial value read/write 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w tcrv0 description clock select bit 2 cks2 0 1 clock input disabled internal clock: ?4, falling edge internal clock: ?8, falling edge internal clock: ?16, falling edge internal clock: ?32, falling edge internal clock: ?64, falling edge internal clock: ?128, falling edge clock input disabled external clock: rising edge external clock: falling edge external clock: rising and falling edges tcrv1 bit 1 cks1 0 1 0 1 bit 0 cks0 0 1 0 1 0 1 0 1 bit 0 icks0 ? 0 1 0 1 0 1 ? ? ? ? counter clear 1 and 0 0 clearing is disabled cleared by compare match a cleared by compare match b cleared by rising edge of external reset input 1 timer overflow interrupt enable 0 interrupt request (ovi) from ovf disabled interrupt request (ovi) from ovf enabled 1 compare match interrupt enable a 0 interrupt request (cmia) from cmfa disabled interrupt request (cmia) from cmfa enabled 1 compare match interrupt enable b 0 interrupt request (cmib) from cmfb disabled interrupt request (cmib) from cmfb enabled 1 378 tcsrv?imer control/status register v h'ffb9 timer v bit initial value read/write 7 cmfb 0 r/(w) 6 cmfa 0 r/(w) 5 ovf 0 r/(w) 4 ? 1 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w output select 0 no change at compare match a 0 output at compare match a 1 output at compare match a output toggles at compare match a 1 0 1 0 1 output select 0 no change at compare match b 0 output at compare match b 1 output at compare match b output toggles at compare match b 1 0 1 0 1 timer overflow flag 0 [clearing condition] after reading ovf = 1, cleared by writing 0 to ovf 1 [setting condition] set when tcntv overflows from h'ff to h'00 compare match flag a 0 [clearing condition] after reading cmfa = 1, cleared by writing 0 to cmfa 1 [setting condition] set when the tcntv value matches the tcora value compare match flag b 0 [clearing condition] after reading cmfb = 1, cleared by writing 0 to cmfb 1 [setting condition] set when the tcntv value matches the tcorb value note: * only a write of 0 for flag clearing is possible. * * * 379 tcora?ime constant register a h'ffba timer v tcorb?ime constant register b h'ffbb timer v tcntv?imer counter v h'ffbc timer v bit initial value read/write 7 tcntv7 0 r/w 6 tcntv6 0 r/w 5 tcntv5 0 r/w 4 tcntv4 0 r/w 3 tcntv3 0 r/w 0 tcntv0 0 r/w 2 tcntv2 0 r/w 1 tcntv1 0 r/w bit initial value read/write 7 tcorb7 1 r/w 6 tcorb6 1 r/w 5 tcorb5 1 r/w 4 tcorb4 1 r/w 3 tcorb3 1 r/w 0 tcorb0 1 r/w 2 tcorb2 1 r/w 1 tcorb1 1 r/w bit initial value read/write 7 tcora7 1 r/w 6 tcora6 1 r/w 5 tcora5 1 r/w 4 tcora4 1 r/w 3 tcora3 1 r/w 0 tcora0 1 r/w 2 tcora2 1 r/w 1 tcora1 1 r/w 380 tcrv1?imer control register v1 h'ffbd timer v bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 4 tveg1 0 r/w 3 tveg0 0 r/w 0 icks0 0 r/w 2 trge 0 r/w 1 ? 1 trgv input enable 0 tcntv counting is not triggered by input at the trgv pin, and does not stop when tcntv is cleared by compare match 1 tcntv counting is triggered by input at the trgv pin, and stops when tcntv is cleared by compare match internal clock select selects the tcntv clock source, with bits cks2 to cks0 in tcrv0 trgv input edge select 0 trgv trigger input is disabled rising edge is selected falling edge is selected rising and falling edges are both selected 1 0 1 0 1 381 382 tcsrw?imer control/status register w h'ffbe watchdog timer bit initial value read/write 7 b6wi 1 r 6 tcwe 0 r/(w) 5 b4wi 1 r 4 tcsrwe 0 r/(w) 3 b2wi 1 r 0 wrst 0 r/(w) 2 wdon 0 r/(w) 1 b0wi 1 r * * * * watchdog timer reset 0 [clearing conditions] 1 [setting condition] when tcw overflows and a reset signal is generated ? reset by res pin ? when tcsrwe = 1, and 0 is written in both b0wi and wrst bit 0 write inhibit 0 bit 0 is write-enabled bit 0 is write-protected 1 watchdog timer on 0 watchdog timer operation is disabled watchdog timer operation is enabled 1 bit 2 write inhibit 0 bit 2 is write-enabled bit 2 is write-protected 1 timer control/status register w write enable 0 data cannot be written to tcsrw bits 2 and 0 data can be written to tcsrw bits 2 and 0 1 bit 4 write inhibit 0 bit 4 is write-enabled bit 4 is write-protected 1 timer counter w write enable 0 data cannot be written to tcw data can be written to tcw 1 bit 6 write inhibit 0 bit 6 is write-enabled bit 6 is write-protected 1 note: * write is permitted only under certain conditions. tcw?imer counter w h'ffbf watchdog timer tmb2?imer mode register b2 h'ffc2 timer b2 bit initial value read/write 7 tmb27 0 r/w 6 ? 1 4 ? 1 3 ? 1 0 tmb20 0 r/w 2 tmb22 0 r/w 1 tmb21 0 r/w 5 ? 1 clock select 0 internal clock: ?2048 internal clock: ?512 internal clock: ?256 internal clock: ?64 internal clock: ?16 internal clock: ?8 internal clock: ?4 reserved 0 1 0 1 0 1 0 0 1 1 1 0 1 auto-reload function select 0 interval timer function selected auto-reload function selected 1 bit initial value read/write 7 tcw7 0 r/w 6 tcw6 0 r/w 5 tcw5 0 r/w 4 tcw4 0 r/w 3 tcw3 0 r/w 0 tcw0 0 r/w 2 tcw2 0 r/w 1 tcw1 0 r/w count value 383 tcb2?imer counter b2 h'ffc3 timer b2 tlb2?imer load register b2 h'ffc3 timer b2 bit initial value read/write 7 tlb27 0 w 6 tlb26 0 w 5 tlb25 0 w 4 tlb24 0 w 3 tlb23 0 w 0 tlb20 0 w 2 tlb22 0 w 1 tlb21 0 w reload value bit initial value read/write 7 tcb27 0 r 6 tcb26 0 r 5 tcb25 0 r 4 tcb24 0 r 3 tcb23 0 r 0 tcb20 0 r 2 tcb22 0 r 1 tcb21 0 r count value 384 amr?/d mode register h'ffc4 a/d converter bit initial value read/write 7 cks 0 r/w 6 trge 0 r/w 4 ? 1 3 ch3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w channel select no channel selected bit 3 0 bit 2 analog input channel ch3 ch2 0 ch1 ch0 bit 1 bit 0 0 an 1 1 0 1 1 * * 1 0 0 external trigger select 0 disables start of a/d conversion by external trigger 1 enables start of a/d conversion by rising or falling edge of external trigger at pin adtrg 5 ? 1 4 an 5 an 6 an 7 reserved * * 1 0 0 1 1 0 1 an 0 an 1 an 2 an 3 clock select 62/ bit 7 0 conversion period cks 31/ 1 31 ? ?= 2 mhz 15.5 ? 12.4 ? ?= 5 mhz * conversion time notes: 1 * 1. don? care operation is not guaranteed if the conversion time is less than 12.4 ?. set bit 7 for a value of at least 12.4 ?. 385 adrr?/d result register h'ffc5 a/d converter adsr?/d start register h'ffc6 a/d converter bit initial value read/write 7 adsf 0 r/w 6 ? 1 5 ? 1 4 ? 1 3 ? 1 0 ? 1 2 ? 1 1 ? 1 a/d status flag 0 1 read write read write indicates completion of a/d conversion stops a/d conversion indicates a/d conversion in progress starts a/d conversion h8/3843 u.m. '93 h'c5 bit initial value read/write 7 adr7 not fixed r 6 adr6 not fixed r 5 adr5 not fixed r 4 adr4 not fixed r 3 adr3 not fixed r 0 adr0 not fixed r 2 adr2 not fixed r 1 adr1 not fixed r a/d conversion result 386 dadr0?/a data register 0 h'ffc8 d/a converter dadr1?/a data register 1 h'ffc9 d/a converter dadr2?/a data register 2 h'ffca d/a converter dadr3?/a data register 3 h'ffcb d/a converter bit initial value read/write 7 dadr37 0 r/w 6 dadr36 0 r/w 5 dadr35 0 r/w 4 dadr34 0 r/w 3 dadr33 0 r/w 0 dadr30 0 r/w 2 dadr32 0 r/w 1 dadr31 0 r/w d/a conversion data bit initial value read/write 7 dadr27 0 r/w 6 dadr26 0 r/w 5 dadr25 0 r/w 4 dadr24 0 r/w 3 dadr23 0 r/w 0 dadr20 0 r/w 2 dadr22 0 r/w 1 dadr21 0 r/w d/a conversion data bit initial value read/write 7 dadr17 0 r/w 6 dadr16 0 r/w 5 dadr15 0 r/w 4 dadr14 0 r/w 3 dadr13 0 r/w 0 dadr10 0 r/w 2 dadr12 0 r/w 1 dadr11 0 r/w d/a conversion data bit initial value read/write 7 dadr07 0 r/w 6 dadr06 0 r/w 5 dadr05 0 r/w 4 dadr04 0 r/w 3 dadr03 0 r/w 0 dadr00 0 r/w 2 dadr02 0 r/w 1 dadr01 0 r/w d/a conversion data 387 dacr0?/a control register 0 h'ffcc d/a converter bit initial value read/write 7 ? 1 r 6 ? 1 r 4 dae0 0 r/w 3 daoe3 0 r/w 0 daoe0 0 r/w 2 daoe2 0 r/w 1 daoe1 0 r/w 5 ? 1 r d/a output enable 1 0 channel 1 analog output disabled (da 1 in high-impedance state) 1 d/a output enable 2 0 channel 2 analog output disabled (da 2 in high-impedance state) 1 d/a output enable 3 0 channel 3 analog output disabled (da 3 in high-impedance state) 1 d/a enable 0 0 d/a conversion disabled on channels 3 to 0 d/a conversion enabled on channels 3 o 0 1 channel 3 analog output enabled channel 2 analog output enabled channel 1 analog output enabled d/a output enable 0 0 channel 0 analog output disabled (da 0 in high-impedance state) 1 channel 0 analog output enabled 388 tmy?imer mode register y h'ffcd timer y bit initial value read/write 7 tmy7 0 r/w 6 ? 1 4 ? 1 3 ? 1 0 tmy0 0 r/w 2 tmy2 0 r/w 1 tmy1 0 r/w 5 ? 1 clock select 0 internal clock: ?8192 internal clock: ?2048 internal clock: ?512 internal clock: ?256 internal clock: ?64 internal clock: ?16 internal clock: ?4 external event (tmiy), rising or falling edge 0 1 0 1 0 1 0 0 1 1 1 0 1 auto-reload function select 0 interval timer function selected auto-reload function selected 1 389 tcyh?imer counter yh h'ffce timer y tlyh?imer load register yh h'ffce timer y tcyl?imer counter yl h'ffcf timer y tlyl?imer load register yl h'ffcf timer y bit initial value read/write 7 tlyl7 0 w 6 tlyl6 0 w 5 tlyl5 0 w 4 tlyl4 0 w 3 tlyl3 0 w 0 tlyl0 0 w 2 tlyl2 0 w 1 tlyl1 0 w reload value bit initial value read/write 7 tlyl7 0 r 6 tlyl6 0 r 5 tlyl5 0 r 4 tlyl4 0 r 3 tlyl3 0 r 0 tlyl0 0 r 2 tlyl2 0 r 1 tlyl1 0 r count value bit initial value read/write 7 tlyh7 0 w 6 tlyh6 0 w 5 tlyh5 0 w 4 tlyh4 0 w 3 tlyh3 0 w 0 tlyh0 0 w 2 tlyh2 0 w 1 tlyh1 0 w reload value bit initial value read/write 7 tcyh7 0 r 6 tcyh6 0 r 5 tcyh5 0 r 4 tcyh4 0 r 3 tcyh3 0 r 0 tcyh0 0 r 2 tcyh2 0 r 1 tcyh1 0 r count value 390 pwcr?wm control register h'ffd0 14-bit pwm pwdru?wm data register u h'ffd1 14-bit pwm pwdrl?wm data register l h'ffd2 14-bit pwm h8/3003 u.m. '93 pwdrl (h'd2) bit initial value read/write 7 0 w 6 0 w 5 0 w 4 0 w 3 0 w 0 0 w 2 0 w 1 0 w lower 8 bits of data for generating pwm waveform pwdrl5 pwdrl4 pwdrl3 pwdrl0 pwdrl2 pwdrl1 pwdrl6 pwdrl7 h8/3003 u.m. '93 pwdru (h'd1) bit initial value read/write 7 1 6 1 5 0 w 4 0 w 3 0 w 0 0 w 2 0 w 1 0 w upper 6 bits of data for generating pwm waveform pwdru5 pwdru4 pwdru3 pwdru0 pwdru2 pwdur1 bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 4 ? 1 3 ? 1 0 pwcr0 0 w 2 ? 1 1 ? 1 clock select 0 the input clock is ?2 (t? = 2/?. the conversion period is 16,384/? with a minimum modulation width of 1/? 1 the input clock is ?4 (t? = 4/?. the conversion period is 32,768/? with a minimum modulation width of 2/? * * note: t? period of pwm input clock * 391 pdr1?ort data register 1 h'ffd4 i/o ports pdr3?ort data register 3 h'ffd6 i/o ports pdr4?ort data register 4 h'ffd7 i/o ports pdr5?ort data register 5 h'ffd8 i/o ports pdr6?ort data register 6 h'ffd9 i/o ports h8/3003 u.m. '93 pdr6 (h'd9) bit initial value read/write 7 p6 0 r/w 6 p6 0 r/w 5 p6 0 r/w 4 p6 0 r/w 3 p6 0 r/w 0 p6 0 r/w 2 p6 0 r/w 1 p6 0 r/w 3 0 2 1 4 5 6 7 h8/3003 u.m. '93 pdr5 (h'd8) bit initial value read/write 7 p5 0 r/w 6 p5 0 r/w 5 p5 0 r/w 4 p5 0 r/w 3 p5 0 r/w 0 p5 0 r/w 2 p5 0 r/w 1 p5 0 r/w 3 0 2 1 4 5 6 7 bit initial value read/write 7 p4 7 0 r/w 6 p4 6 0 r/w 5 p4 5 0 r/w 4 p4 4 0 r/w 3 p4 0 r/w 0 p4 0 r/w 2 p4 0 r/w 1 p4 0 r/w 3 0 2 1 h8/3003 u.m. '93 pdr3 (h'd6) bit initial value read/write 7 p3 0 r/w 6 p3 0 r/w 5 p3 0 r/w 4 p3 0 r/w 3 p3 0 r/w 0 p3 0 r/w 2 p3 0 r/w 1 p3 0 r/w 7 6 5 4 3 0 2 1 h8/3003 u.m. '93 pwdrl (h'd2) bit initial value read/write 7 p1 0 r/w 6 p1 0 r/w 5 p1 0 r/w 4 p1 0 r/w 3 p1 0 r/w 0 p1 0 r/w 2 p1 0 r/w 1 p1 0 r/w 7 6 5 4 3 0 2 1 392 pdr7?ort data register 7 h'ffda i/o ports pdr8?ort data register 8 h'ffdb i/o ports pdrb?ort data register b h'ffdd i/o ports pdrc?ort data register c h'ffde i/o ports h8/3003 u.m. '93 pdrc (h'df) bit initial value read/write 7 6 5 4 3 pc r 0 pc r 2 pc r 1 pc r 3 0 2 1 h8/3003 u.m. '93 pdrb (h'de) bit initial value read/write 7 pb r 6 pb r 5 pb r 4 pb r 3 pb r 0 pb r 2 pb r 1 pb r 3 0 2 1 4 5 6 7 h8/3003 u.m. '93 pdr8 (h'db) bit initial value read/write 7 p8 0 r/w 6 p8 0 r/w 5 p8 0 r/w 4 p8 0 r/w 3 p8 0 r/w 0 p8 0 r/w 2 p8 0 r/w 1 p8 0 r/w 3 0 2 1 4 5 6 7 h8/3003 u.m. '93 pdr7 (h'da) bit initial value read/write 7 p7 0 r/w 6 p7 0 r/w 5 p7 0 r/w 4 p7 0 r/w 3 p7 0 r/w 0 p7 0 r/w 2 p7 0 r/w 1 p7 0 r/w 3 0 2 1 4 5 6 7 393 394 tmb3?imer mode register b3 h'ffe2 timer b3 tcb3?imer counter b3 h'ffe3 timer b3 tlb3?imer load register b3 h'ffe3 timer b3 bit initial value read/write 7 tlb37 0 w 6 tlb36 0 w 5 tlb35 0 w 4 tlb34 0 w 3 tlb33 0 w 0 tlb30 0 w 2 tlb32 0 w 1 tlb31 0 w reload value bit initial value read/write 7 tcb37 0 r 6 tcb36 0 r 5 tcb35 0 r 4 tcb34 0 r 3 tcb33 0 r 0 tcb30 0 r 2 tcb32 0 r 1 tcb31 0 r count value bit initial value read/write 7 tmb37 0 r/w 6 ? 1 4 ? 1 3 ? 1 0 tmb30 0 r/w 2 tmb32 0 r/w 1 tmb31 0 r/w 5 ? 1 clock select 0 internal clock: ?2048 internal clock: ?512 internal clock: ?256 internal clock: ?64 internal clock: ?16 internal clock: ?8 internal clock: ?4 reserved 0 1 0 1 0 1 0 0 1 1 1 0 1 auto-reload function select 0 interval timer function selected auto-reload function selected 1 pcr1?ort control register 1 h'ffe4 i/o ports pcr3?ort control register 3 h'ffe6 i/o ports pcr4?ort control register 4 h'ffe7 i/o ports bit initial value read/write 7 pcr4 7 0 w 6 pcr4 6 0 w 5 pcr4 5 0 w 4 pcr4 4 0 w 3 pcr4 3 0 w 0 pcr4 0 w 2 pcr4 0 w 1 pcr4 0 w port 4 input/output select 0 input pin 1 output pin 0 2 1 h8/3003 u.m. '93 pcr3 (h'e6) bit initial value read/write 7 pcr3 0 w 6 pcr3 0 w 5 pcr3 0 w 4 pcr3 0 w 3 pcr3 0 w 0 pcr3 0 w 2 pcr3 0 w 1 pcr3 0 w port 3 input/output select 0 input pin 1 output pin 7 6 5 4 3 0 2 1 h8/3003 u.m. '93 pcr1 (h'e4) bit initial value read/write 7 pcr1 0 w 6 pcr1 0 w 5 pcr1 0 w 4 pcr1 0 w 3 pcr1 0 w 0 pcr1 0 w 2 pcr1 0 w 1 pcr1 0 w port 1 input/output select 0 input pin 1 output pin 7 6 5 4 3 0 2 1 395 pcr5?ort control register 5 h'ffe8 i/o ports pcr6?ort control register 6 h'ffe9 i/o ports pcr7?ort control register 7 h'ffea i/o ports h8/3003 u.m. '93 pcr7 (h'ea) bit initial value read/write 7 pcr7 0 w 6 pcr7 0 w 5 pcr7 0 w 4 pcr7 0 w 3 pcr7 0 w 0 pcr7 0 w 2 pcr7 0 w 1 pcr7 0 w port 7 input/output select 0 input pin 1 output pin 7 6 5 4 3 0 2 1 h8/3003 u.m. '93 pcr5 (h'e8) bit initial value read/write 7 pcr6 0 w 6 pcr6 0 w 5 pcr6 0 w 4 pcr6 0 w 3 pcr6 0 w 0 pcr6 0 w 2 pcr6 0 w 1 pcr6 0 w port 6 input/output select 0 input pin 1 output pin 7 6 5 4 3 0 2 1 h8/3003 u.m. '93 pcr5 (h'e8) bit initial value read/write 7 pcr5 0 w 6 pcr5 0 w 5 pcr5 0 w 4 pcr5 0 w 3 pcr5 0 w 0 pcr5 0 w 2 pcr5 0 w 1 pcr5 0 w port 5 input/output select 0 input pin 1 output pin 7 6 5 4 3 0 2 1 396 pcr8?ort control register 8 h'ffeb i/o ports pucr1?ort pull-up control register 1 h'ffed i/o ports pucr3?ort pull-up control register 3 h'ffee i/o ports pucr5?ort pull-up control register 5 h'ffef i/o ports h8/3003 u.m. '93 pucr5 (h'e2) bit initial value read/write 7 pucr5 0 r/w 6 pucr5 0 r/w 5 pucr5 0 r/w 4 pucr5 0 r/w 3 pucr5 0 r/w 0 pucr5 0 r/w 2 pucr5 0 r/w 1 pucr5 0 r/w 3 0 2 1 4 5 6 7 h8/3003 u.m. '93 pucr3 (h'e1) bit initial value read/write 7 pucr3 0 r/w 6 pucr3 0 r/w 5 pucr3 0 r/w 4 pucr3 0 r/w 3 pucr3 0 r/w 0 pucr3 0 r/w 2 pucr3 0 r/w 1 pucr3 0 r/w 3 0 2 1 4 5 6 7 h8/3003 u.m. '93 pucr1 (h'e0) bit initial value read/write 7 pucr1 0 r/w 6 pucr1 0 r/w 5 pucr1 0 r/w 4 pucr1 0 r/w 3 pucr1 0 r/w 0 pucr1 0 r/w 2 pucr1 0 r/w 1 pucr1 0 r/w 3 0 2 1 4 5 6 7 h8/3003 u.m. '93 pcr8 (h'eb) bit initial value read/write 7 pcr8 0 w 6 pcr8 0 w 5 pcr8 0 w 4 pcr8 0 w 3 pcr8 0 w 0 pcr8 0 w 2 pcr8 0 w 1 pcr8 0 w port 8 input/output select 0 input pin 1 output pin 7 6 5 4 3 0 2 1 397 syscr1?ystem control register 1 h'fff0 system control bit initial value read/write 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 3 lson 0 r/w 0 ? 1 2 ? 1 1 ? 1 4 sts0 0 r/w software standby 0 ? when a sleep instruction is executed in active mode, a transition is made to sleep mode 1 standby timer select 2 to 0 0 wait time = 8,192 states wait time = 16,384 states 0 0 1 wait time = 32,768 states wait time = 65,536 states 1 0 1 1 * wait time = 131,072 states low speed on flag 0 the cpu operates on the system clock (? 1 the cpu operates on the subclock (? ) sub * ? when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode ? when a sleep instruction is executed in active mode, a transition is made to standby mode or watch mode ? when a sleep instruction is executed in subactive mode, a transition is made to watch mode note: don? care * 398 syscr2?ystem control register 2 h'fff1 system control bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 3 dton 0 r/w 0 sa0 0 r/w 2 mson 0 r/w 1 sa1 0 r/w 4 nesel 0 r/w subactive mode clock select 0 ? /8 ? /4 0 1 1 ? /2 * w w w direct transfer on flag 0 ? when a sleep instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode 1 ? when a sleep instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode ? when a sleep instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if ssby = 0, mson = 1, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 ? when a sleep instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if ssby = 0, mson = 0, and lson = 0, or to subactive mode if ssby = 1, tma3 = 1, and lson = 1 ? when a sleep instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 0, or to active (medium-speed) mode if ssby = 1, tma3 = 1, lson = 0, and mson = 1 medium speed on flag 0 ? operates in active (high-speed) mode after exit from standby, watch, or sleep mode ? operates in sleep (high-speed) mode if a sleep instruction is executed in active mode 1 ? operates in active (medium-speed) mode after exit from standby, watch, or sleep mode ? operates in sleep (medium-speed) mode if a sleep instruction is executed in active mode noise elimination sampling frequency select 0 sampling rate is ? /16 1 sampling rate is ? /4 osc osc note: don? care * 399 iegr1?nterrupt edge select register 1 h'fff2 system control bit initial value read/write 7 nmieg 0 r/w 6 ? 1 4 ? 1 3 ieg3 0 r/w 0 ieg0 0 r/w 2 ieg2 0 r/w 1 ieg1 0 r/w 5 ? 1 irq 0 edge select 0 falling edge of irq 0 pin input is detected rising edge of irq 0 pin input is detected 1 irq 1 edge select 0 falling edge of irq 1 pin input is detected rising edge of irq 1 pin input is detected 1 irq 2 edge select 0 falling edge of irq 2 pin input is detected rising edge of irq 2 pin input is detected 1 irq 3 edge select 0 falling edge of irq 3 pin input is detected rising edge of irq 3 pin input is detected 1 nmi edge select 0 falling edge of nmi pin input is detected rising edge of nmi pin input is detected 1 400 iegr2?nterrupt edge select register 2 h'fff3 system control bit initial value read/write 7 integ7 0 r/w 6 integ6 0 r/w 4 integ4 0 r/w 3 integ3 0 r/w 0 integ0 0 r/w 2 integ2 0 r/w 1 integ1 0 r/w 5 integ5 0 r/w int 5 to int 0 edge select 0 falling edge of int n pin input is detected rising edge of int n pin input is detected 1 int 6 edge select 0 falling edge of int 6 and tmib pin input is detected rising edge of int 6 and tmib pin input is detected 1 int 7 edge select 0 falling edge of int 7 and tmiy pin input is detected rising edge of int 7 and tmiy pin input is detected 1 (n = 5 to 0) 401 ienr1?nterrupt enable register 1 h'fff4 system control bit initial value read/write 7 ientb1 0 r/w 6 ienta 0 r/w 4 ? 1 3 ien3 0 r/w 0 ien0 0 r/w 2 ien2 0 r/w 1 ien1 0 r/w 5 ienty 0 r/w irq 3 to irq 0 interrupt enable 0 disables irq3 to irq 0 interrupt requests enables irq3 to irq 0 interrupt requests 1 timer a interrupt enable 0 disables timer a interrupt requests enables timer a interrupt requests 1 timer b1 interrupt enable 0 disables timer b1 interrupt requests enables timer b1 interrupt requests 1 timer y interrupt enable 0 disables timer y interrupt requests enables timer y interrupt requests 1 402 ienr2?nterrupt enable register 2 h'fff5 system control bit initial value read/write 7 iendt 0 r/w 6 ienad 0 r/w 4 iens1 0 r/w 3 iente 0 r/w 0 ientb2 0 r/w 2 ientc 0 r/w 1 ientb3 0 r/w 5 iens2 0 r/w timer b2 interrupt enable 0 disables timer b2 interrupt requests enables timer b2 interrupt requests 1 timer c interrupt enable 0 disables timer c interrupt requests enables timer c interrupt requests 1 timer e interrupt enable 0 disables timer e interrupt requests enables timer e interrupt requests 1 timer b3 interrupt enable 0 disables timer b3 interrupt requests enables timer b3 interrupt requests 1 sci1 interrupt enable 0 disables sci1 interrupt requests enables sci1 interrupt requests 1 sci2 interrupt enable 0 disables sci2 interrupt requests enables sci2 interrupt requests 1 a/d converter interrupt enable 0 disables a/d converter interrupt requests enables a/d converter interrupt requests 1 direct transfer interrupt enable 0 disables direct transfer interrupt requests enables direct transfer interrupt requests 1 403 ienr3?nterrupt enable register 3 h'fff6 system control bit initial value read/write 7 inten7 0 r/w 6 inten6 0 r/w 5 inten5 0 r/w 4 inten4 0 r/w 3 inten3 0 r/w 0 inten0 0 r/w 2 inten2 0 r/w 1 inten1 0 r/w int 7 to int 0 interrupt enable 0 disables int 7 to int 0 interrupt requests enables int 7 to int 0 interrupt requests 1 404 irr1?nterrupt request register 1 h'fff7 system control bit initial value read/write 7 irrtb1 0 r/w 6 irrta 0 r/w 4 ? 1 3 irri3 0 r/w 0 irri0 0 r/w 2 irri2 0 r/w 1 irri1 0 r/w 5 irrty 0 r/w * * * * * * * irq 3 to irq 0 interrupt request flag 0 [clearing condition] 1 [setting condition] when irrin = 1, it is cleared by writing 0 when pin irqn is set for interrupt input and the designated signal edge is input timer y interrupt request flag 0 [clearing condition] 1 [setting condition] when irrty = 1, it is cleared by writing 0 when timer counter y overflows from h'ffff to h'0000 timer a interrupt request flag 0 [clearing condition] 1 [setting condition] when irrta = 1, it is cleared by writing 0 when timer counter a overflows from h'ff to h'00 timer b1 interrupt request flag 0 [clearing condition] 1 [setting condition] when irrtb1 = 1, it is cleared by writing 0 when timer counter b1 overflows from h'ff to h'00 note: * only a write of 0 for flag clearing is possible. (n = 3 to 0) 405 406 irr2?nterrupt request register 2 h'fff8 system control bit initial value read/write 7 irrdt 0 r/w 6 irrad 0 r/w 5 irrs2 0 r/w 4 irrs1 0 r/w 3 irrte 0 r/w 0 irrtb2 0 r/w 2 irrtc 0 r/w 1 irrtb3 0 r/w * * * * * * * 0 [clearing condition] when irrtb3 = 1, it is cleared by writing 0 timer b3 interrupt request flag 1 [setting condition] when timer counter b3 overflows from h'ff to h'00 0 [clearing condition] when irrtb2 = 1, it is cleared by writing 0 1 [setting condition] when timer counter b2 overflows from h'ff to h'00 timer b2 interrupt request flag 0 [clearing condition] when irrtc = 1, it is cleared by writing 0 timer c interrupt request flag 1 [setting condition] when timer counter c overflows from h'ff to h'00 0 [clearing condition] when irrte = 1, it is cleared by writing 0 timer e interrupt request flag 1 [setting condition] when timer counter e overflows from h'ff to h'00 0 [clearing condition] when irrs1 = 1, it is cleared by writing 0 sci1 interrupt request flag 1 [setting condition] when an sci1 transfer is completed 0 [clearing condition] when irrs2 = 1, it is cleared by writing 0 sci2 interrupt request flag 1 [setting condition] when an sci2 transfer is completed or aborted 0 [clearing condition] when irrad = 1, it is cleared by writing 0 a/d converter interrupt request flag 1 [setting condition] when a/d conversion is completed and adsf is cleared to 0 in adsr 0 [clearing condition] when irrdt = 1, it is cleared by writing 0 direct transfer interrupt request flag 1 [setting condition] a sleep instruction is executed when dton = 1 and a direct transfer is made note: * only a write of 0 for flag clearing is possible. * irr3?nterrupt request register 3 h'fff9 system control bit initial value read/write 7 intf7 0 r/w 6 intf6 0 r/w 5 intf5 0 r/w 4 intf4 0 r/w 3 intf3 0 r/w 0 intf0 0 r/w 2 intf2 0 r/w 1 intf1 0 r/w int 7 to int 0 interrupt request flag 0 [clearing condition] when intf n = 1, it is cleared by writing 0 1 [setting condition] when the designated signal edge is input at pin int n note: * only a write of 0 for flag clearing is possible. * * * * * * * (n = 7 to 0) 407 pmr1?ort mode register 1 h'fffc i/o ports bit initial value read/write 7 irq3 0 r/w 6 irq2 0 r/w 4 pwm 0 r/w 3 tciceg 0 r/w 0 tmow 0 r/w 2 ? 1 1 tmoe 0 r/w 5 irq1 0 r/w p1 0 /tmow pin function switch 0 functions as p1 0 i/o pin functions as tmow output pin 1 tmic edge select 0 falling edge of tmic pin input is detected rising edge of tmic pin input is detected 1 p1 1 /tmoe pin function switch 0 functions as p1 1 i/o pin functions as tmoe output pin 1 p1 4 /pwm pin function switch 0 functions as p1 4 i/o pin functions as pwm output pin 1 p1 5 /irq 1 pin function switch 0 functions as p1 5 i/o pin functions as irq 1 input pin 1 p1 6 /irq 2 pin function switch 0 functions as p1 6 i/o pin functions as irq 2 input pin 1 p1 7 /irq 3 pin function switch 0 functions as p1 7 i/o pin functions as irq 3 /trgv input pin 1 408 pmr3?ort mode register 3 h'fffd i/o ports bit initial value read/write 7 cs 0 r/w 6 strb 0 r/w 4 si2 0 r/w 3 sck2 0 r/w 0 sck1 0 r/w 2 so1 0 r/w 1 si1 0 r/w 5 so2 0 r/w p3 0 /sck 1 pin function switch 0 functions as p3 0 i/o pin functions as sck 1 i/o pin 1 p3 2 /so 1 pin function switch 0 functions as p3 2 i/o pin functions as so 1 output pin 1 p3 3 /sck 2 pin function switch 0 functions as p3 3 i/o pin functions as sck 2 i/o pin 1 p3 1 /si 1 pin function switch 0 functions as p3 1 i/o pin functions as si 1 input pin 1 p3 4 /si 2 pin function switch 0 functions as p3 4 i/o pin functions as si 2 input pin 1 p3 5 /so 2 pin function switch 0 functions as p3 5 i/o pin functions as so 2 output pin 1 p3 6 /strb pin function switch 0 functions as p3 6 i/o pin functions as strb output pin 1 p3 7 / cs pin function switch 0 functions as p3 7 i/o pin functions as cs input pin 1 409 rter?ealtime enable register h'fffe i/o ports pmr7?ort mode register 7 h'ffff i/o ports bit initial value read/write 7 ? 1 6 ? 1 5 ? 1 4 ? 1 3 ? 1 0 rof1 0 r/w 2 ? 1 1 rof2 0 r/w p3 2 /so 1 pin pmos control 0 cmos output nmos open-drain output 1 p3 5 /so 2 pin pmos control 0 cmos output nmos open-drain output 1 bit initial value read/write 7 rter 7 0 r/w 6 rter 6 0 r/w 5 rter 5 0 r/w 4 rter 4 0 r/w 3 rter 3 0 r/w 0 rter 0 0 r/w 2 rter 2 0 r/w 1 rter 1 0 r/w p6 n /rp n pin function switch 0 functions as p6 n i/o pin functions as rp n output pin 1 (n = 7 to 0) 410 appendix c i/o port block diagrams c.1 block diagrams of port 1 figure c-1 (a) port 1 block diagram (pins p1 7 and p1 6 ) v cc v cc v ss pucr1 n pmr1 n pdr1 n pcr1 n irq n? res sby (low level during reset and in standby mode) internal data bus pdr1: pcr1: pmr1: pucr1: n = 7 or 6 port data register 1 port control register 1 port mode register 1 port pull-up control register 1 p1 n 411 figure c-1 (b) port 1 block diagram (pin p1 5 ) v cc v cc v ss pucr1 5 pmr1 5 pdr1 5 pcr1 5 irq 1 res sby (low level during reset and in standby mode) internal data bus pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 p1 5 412 figure c-1 (c) port 1 block diagram (pin p1 4 ) v cc v cc v ss pucr1 4 pmr1 4 pdr1 4 pcr1 4 res sby (low level during reset and in standby mode) internal data bus pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 pwm pwm module p1 4 413 figure c-1 (d) port 1 block diagram (pin p1 3 ) v cc v cc v ss pucr1 3 pmr1 3 pdr1 3 pcr1 3 tmic res sby internal data bus pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 p1 3 (low level during reset and in standby mode) edge select timer c module 414 figure c-1 (e) port 1 block diagram (pin p1 2 ) v cc v cc v ss pucr1 2 pdr1 2 pcr1 2 ud res sby internal data bus pdr1: pcr1: pucr1: port data register 1 port control register 1 port pull-up control register 1 p1 2 (low level during reset and in standby mode) timer c module 415 figure c-1 (f) port 1 block diagram (pin p1 1 ) v cc v cc v ss pucr1 1 pmr1 1 pdr1 1 pcr1 1 res sby internal data bus pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 tmoe timer e module p1 1 (low level during reset and in standby mode) 416 figure c-1 (g) port 1 block diagram (pin p1 0 ) v cc v cc v ss pucr1 0 pmr1 0 pdr1 0 pcr1 0 res sby internal data bus pdr1: pcr1: pmr1: pucr1: port data register 1 port control register 1 port mode register 1 port pull-up control register 1 tmow timer a module p1 0 (low level during reset and in standby mode) 417 c.2 block diagrams of port 3 figure c-2 (a) port 3 block diagram (pin p3 7 ) v cc v cc v ss pucr3 7 pmr3 7 pdr3 7 pcr3 7 res sby (low level during reset and in standby mode) internal data bus pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 p3 7 cs sci2 module 418 figure c-2 (b) port 3 block diagram (pin p3 6 ) v cc v cc v ss pucr3 6 pmr3 6 pdr3 6 pcr3 6 res sby (low level during reset and in standby mode) internal data bus pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 strb sci2 module p3 6 419 figure c-2 (c) port 3 block diagram (pin p3 5 ) v cc v cc v ss pucr3 5 pmr3 5 pdr3 5 pcr3 5 res sby (low level during reset and in standby mode) internal data bus pdr3: pcr3: pmr3: pmr7: pucr3: port data register 3 port control register 3 port mode register 3 port mode register 7 port pull-up control register 3 so2 sci2 module p3 5 pmr7 1 abt 420 figure c-2 (d) port 3 block diagram (pin p3 4 ) v cc v cc v ss pucr3 4 pdr3 4 pcr3 4 si2 res sby internal data bus pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 p3 4 (low level during reset and in standby mode) sci2 module pmr3 4 421 figure c-2 (e) port 3 block diagram (pin p3 3 ) v cc v cc v ss pucr3 3 pmr3 3 pdr3 3 pcr3 3 res sby pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 sci2 module p3 3 (low level during reset and in standby mode) cks2 to cks0 abt sck0 sck1 internal data bus 422 figure c-2 (f) port 3 block diagram (pin p3 2 ) v cc v cc v ss pucr3 2 pmr3 2 pdr3 2 pcr3 2 res sby (low level during reset and in standby mode) internal data bus pdr3: pcr3: pmr3: pmr7: pucr3: port data register 3 port control register 3 port mode register 3 port mode register 7 port pull-up control register 3 so1 sci1 module p3 2 pmr7 0 423 figure c-2 (g) port 3 block diagram (pin p3 1 ) v cc v cc v ss pucr3 1 pdr3 1 pcr3 1 si1 res sby internal data bus pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 p3 1 (low level during reset and in standby mode) sci1 module pmr3 1 424 figure c-2 (h) port 3 block diagram (pin p3 0 ) v cc v cc v ss pucr3 0 pmr3 0 pdr3 0 pcr3 0 res sby pdr3: pcr3: pmr3: pucr3: port data register 3 port control register 3 port mode register 3 port pull-up control register 3 sci1 module p3 0 (low level during reset and in standby mode) cks3 sck1 internal data bus sck0 425 c.3 block diagram of port 4 figure c-3 port 4 block diagram (pins p4 7 to p4 0 ) v cc v ss pdr4 n pcr4 n sby internal data bus pdr4: pcr4: n = 7 to 0 port data register 4 port control register 4 p4 n (low level during reset and in standby mode) 426 c.4 block diagrams of port 5 figure c-4 (a) port 5 block diagram (pin p5 7 ) v cc v cc v ss int 7 res sby internal data bus pdr5: pcr5: pucr5: port data register 5 port control register 5 port pull-up control register 5 p5 7 (low level during reset and in standby mode) int module pucr5 7 pdr5 7 pcr5 7 tmiy timer y module 427 figure c-4 (b) port 5 block diagram (pin p5 6 ) v cc v cc v ss int 6 sby internal data bus pdr5: pcr5: pucr5: port data register 5 port control register 5 port pull-up control register 5 p5 6 (low level during reset and in standby mode) int module pucr5 6 pdr5 6 pcr5 6 tmib timer b1 module 428 figure c-4 (c) port 5 block diagram (pin p5 5 ) v cc v cc v ss int 5 res sby internal data bus pdr5: pcr5: pucr5: port data register 5 port control register 5 port pull-up control register 5 p5 5 (low level during reset and in standby mode) int module pucr5 5 pdr5 5 pcr5 5 adtrg a/d module 429 figure c-4 (d) port 5 block diagram (pins p5 4 to p5 0 ) v cc v cc v ss int n res sby internal data bus pdr5: pcr5: pucr5: n = 4 to 0 port data register 5 port control register 5 port pull-up control register 5 p5 n (low level during reset and in standby mode) int module pucr5 n pdr5 n pcr5 n 430 c.5 block diagram of port 6 figure c-5 port 6 block diagram (pins p6 7 to p6 0 ) v cc v ss trgv sby internal data bus pdr6: pcr6: rter: pdrs: pcrs: n = 7 to 0 port data register 6 port control register 6 realtime enable register port data register slave port control register slave p6 n (low level during reset and in standby mode) pdrs n pcrs n pcr6 n pdr6 n rter n ck ck 431 c.6 block diagrams of port 7 figure c-6 (a) port 7 block diagram (pins p7 7 and p7 3 to p7 0 ) v cc v ss sby internal data bus pdr7: pcr7: n = 7, 3 to 0 port data register 7 port control register 7 p7 n (low level during reset and in standby mode) pdr7 n pcr7 n 432 figure c-6 (b) port 7 block diagram (pin p7 6 ) v cc v ss sby internal data bus pdr7: pcr7: port data register 7 port control register 7 p7 6 (low level during reset and in standby mode) pdr7 6 pcr7 6 0s3 to 0s0 tmov timer v module 433 figure c-6 (c) port 7 block diagram (pin p7 5 ) v cc v ss sby internal data bus pdr7: pcr7: port data register 7 port control register 7 p7 5 (low level during reset and in standby mode) pdr7 5 pcr7 5 tmciv timer v module 434 figure c-6 (d) port 7 block diagram (pin p7 4 ) v cc v ss sby internal data bus pdr7: pcr7: port data register 7 port control register 7 p7 4 (low level during reset and in standby mode) pdr7 4 pcr7 4 tmriv timer v module 435 c.7 block diagrams of port 8 figure c-7 (a) port 8 block diagram (pin p8 7 ) v cc v ss sby internal data bus pdr8: pcr8: port data register 8 port control register 8 p8 7 (low level during reset and in standby mode) pdr8 7 pcr8 7 436 figure c-7 (b) port 8 block diagram (pin p8 6 ) v cc v ss sby internal data bus pdr8: pcr8: port data register 8 port control register 8 p8 6 (low level during reset and in standby mode) pdr8 6 pcr8 6 ftid timer x module 437 figure c-7 (c) port 8 block diagram (pin p8 5 ) v cc v ss sby internal data bus pdr8: pcr8: port data register 8 port control register 8 p8 5 (low level during reset and in standby mode) pdr8 5 pcr8 5 ftic timer x module 438 figure c-7 (d) port 8 block diagram (pin p8 4 ) v cc v ss sby internal data bus pdr8: pcr8: port data register 8 port control register 8 p8 4 (low level during reset and in standby mode) pdr8 4 pcr8 4 ftib timer x module 439 figure c-7 (e) port 8 block diagram (pin p8 3 ) v cc v ss sby internal data bus pdr8: pcr8: port data register 8 port control register 8 p8 3 (low level during reset and in standby mode) pdr8 3 pcr8 3 ftia timer x module 440 figure c-7 (f) port 8 block diagram (pin p8 2 ) v cc v ss sby internal data bus pdr8: pcr8: port data register 8 port control register 8 p8 2 (low level during reset and in standby mode) pdr8 2 pcr8 2 oeb ftob timer x module 441 figure c-7 (g) port 8 block diagram (pin p8 1 ) v cc v ss sby internal data bus pdr8: pcr8: port data register 8 port control register 8 p8 1 (low level during reset and in standby mode) pdr8 1 pcr8 1 oea ftoa timer x module 442 figure c-7 (h) port 8 block diagram (pin p8 0 ) v cc v ss sby internal data bus pdr8: pcr8: port data register 8 port control register 8 p8 0 (low level during reset and in standby mode) pdr8 0 pcr8 0 ftci timer x module p8 0 443 c.8 block diagram of port b figure c-8 port b block diagram (pins pb 7 to pb 0 ) pb n internal data bus amr3 to amr0 a/d module an n n = 7 to 0 dec 444 c.9 block diagram of port c figure c-9 port c block diagram (pins pc 3 to pc 0 ) pc n internal data bus daoe3 to daoe0 d/a module da n n = 3 to 0 dec dae0 445 appendix d port states in the different processing states table d-1 port states overview port reset sleep subsleep standby watch subactive active p1 7 to p1 0 high retained retained high retained functions functions impedance impedance * p3 7 to p3 0 high retained retained high retained functions functions impedance impedance * p4 3 to p4 0 high retained retained high retained functions functions impedance impedance p5 7 to p5 0 high retained retained high retained functions functions impedance impedance * p6 7 to p6 0 high retained retained high retained functions functions impedance impedance * p7 7 to p7 0 high retained retained high retained functions functions impedance impedance p8 7 to p8 0 high retained retained high retained functions functions impedance impedance pb 7 to pb 0 high high high high high high high impedance impedance impedance impedance impedance impedance impedance pc 3 to pc 0 high high high high high high high impedance impedance impedance impedance impedance impedance impedance note: * high level output when mos pull-up is in on state. 446 appendix e package dimensions dimensional drawings of h8/3927 packages fp-80b and tfp-80f are shown in figures e-1 and e-2 below. unit: mm 447 60 0 ?5 0.10 0.12 m 17.2 ?0.3 41 61 80 1 20 40 21 17.2 ?.3 0.30 ?.10 0.65 3.05 max 0.10 1.60 0.80 ?0.30 14.0 2.70 +0.20 ?.16 0.17 +0.08 ?.05 figure e-1 fp-80b package dimensions unit: mm 448 0.10 0.13 m 16.0 ?0.2 0.00 min 0.20 max 1.20 max 0.17 ?0.05 0.65 0.50 ?0.10 16.0 ?0.2 60 41 80 1 21 40 20 0 ?5 14.0 61 1.00 0.30 ?0.10 figure e-2 tfp-80f package dimensions note: in case of inconsistencies arising within figures, dimensional drawings listed in the hitachi semiconductor packages manual take precedence and are considered correct. |
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